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CH572D (QFN-20-EP(3x3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH572D

WCHID: C46597863QFN-20-EP(3x3) · 21 Pins · Pitch 0.50mmDISCREPANCY REVIEW REQUIRED5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH572D (QFN-20-EP(3x3))1VDD332PA03PA14PA75ANT6XI7GND8V59PA910PA811PA021ep20PA219NC18PA11/R7/T617PA10/R6/T716PA715PA614PA513PA412PA1Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.220.315.210.25.10-5.1-10.2-15.2-20.3mm
2. 2D FOOTPRINT
123456789101112131415161718192021E=3.00mm · Pitch e=0.50mmD=3.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.00mm × 3.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (21/21)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
2PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, I2C, SWD/JTAG)
3PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, I2C, SWD/JTAG)
4PA7I/OMultiplexed I/O & Peripheral Pin PA7 (UART, SPI, PWM)
5ANTI/OMultiplexed I/O & Peripheral Pin ANT (General)
6XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
7GNDGNDGround Reference Pin (GND)
8V5I/OMultiplexed I/O & Peripheral Pin V5 (General)
9PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, I2C)
10PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, I2C, PWM)
11PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, SWD/JTAG)
12PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, I2C, SWD/JTAG)
13PA4I/OMultiplexed I/O & Peripheral Pin PA4 (PWM)
14PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, I2C)
15PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, I2C)
16PA7I/OMultiplexed I/O & Peripheral Pin PA7 (UART, SPI, PWM)
17PA10/R6/T7I/OMultiplexed I/O & Peripheral Pin PA10/R6/T7 (General)
18PA11/R7/T6I/OMultiplexed I/O & Peripheral Pin PA11/R7/T6 (General)
19NCI/OMultiplexed I/O & Peripheral Pin NC (General)
20PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, I2C)
21epGNDExposed Thermal & Ground Pad (ep)
PIN 1 VDD33
Power
Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
Design note: 如果是单 一3 .3V电源供电 ，则VDD33引脚输入额定3 .3V 电源 V5引脚悬空或与VDD33引脚短接 ， 。
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH572D (WCH · QFN-20-EP(3x3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH572D (QFN-20-EP(3x3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH572D (QFN-20-EP(3x3)) - 2. Standard Pinout (Top View)
True package pinout (21 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH572D (QFN-20-EP(3x3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH572D (QFN-20-EP(3x3)) - 4. Package Dimensions (D×E×A)
QFN-20-EP(3x3) · 3.00×3.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH572D (QFN-20-EP(3x3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (21 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH572D (QFN-20-EP(3x3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH570 / CH572
P1 · p01_fig01247×133px
CH572D (QFN-20-EP(3x3)) — 概述
概述
P3 · p03_fig011459×1448px
CH572D (QFN-20-EP(3x3)) — CH572R
CH572R
P3 · p03_fig02893×576px
CH572D (QFN-20-EP(3x3)) — V1.0 1
V1.0 1
P4 · p04_fig011266×490px
CH572D (QFN-20-EP(3x3)) — CH572/CH570 数据手册 https://wch.cn
CH572/CH570 数据手册 https://wch.cn
P4 · p04_fig021462×1943px
CH572D (QFN-20-EP(3x3)) — V1.0 2
V1.0 2
P4 · p04_fig01P4
CH572D (QFN-20-EP(3x3)) — Datasheet Page 4 (p04_fig01)
Datasheet Page 4 (p04_fig01)

Technical Specifications & Part Details (CH572D)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH572D (QFN-20-EP(3x3)) is a 20-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, SPI, I2C, PWM, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
16MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-20-EP(3x3))
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, SPI, I2C, PWM, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol21 auto-grouped pins
OK
IPC-7351B Land Pattern21 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 1.70×1.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-20-EP(3x3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
21P / 21Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-20-EP(3x3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH572D (QFN-20-EP(3x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH572D (QFN-20-EP(3x3))?

Manufactured by WCH, the CH572D is housed in a QFN-20-EP(3x3) package with 21 pins and a 0.50 mm lead pitch. Key pins include: 1 (VDD33: Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)), 2 (PA0: Multiplexed I/O & Peripheral Pin PA0 (UART, I2C, SWD/JTAG)), 3 (PA1: Multiplexed I/O & Peripheral Pin PA1 (UART, I2C, SWD/JTAG)), 4 (PA7: Multiplexed I/O & Peripheral Pin PA7 (UART, SPI, PWM)), 5 (ANT: Multiplexed I/O & Peripheral Pin ANT (General)), 6 (XI: Multiplexed I/O & Peripheral Pin XI (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for CH572D?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH572D (QFN-20-EP(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 1.70 × 1.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH572D?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH572D (WCH, QFN-20-EP(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (21 pins) & CH570 / CH572 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2PA0Digital_IOSignal terminal PA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, I2C, SWD/JTAG.
3PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, I2C, SWD/JTAG.
4PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7. Supported peripheral buses: UART, SPI, PWM.
5ANTRF_50OhmSignal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General.
6XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
7GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
8V5Digital_IOSignal terminal V5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V5. Supported peripheral buses: General.
9PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, I2C.
10PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, I2C, PWM.
11PA0Digital_IOSignal terminal PA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, SWD/JTAG.
12PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, I2C, SWD/JTAG.
13PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4. Supported peripheral buses: PWM.
14PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5. Supported peripheral buses: SPI, I2C.
15PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6. Supported peripheral buses: UART, SPI, I2C.
16PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7. Supported peripheral buses: UART, SPI, PWM.
17PA10/R6/T7Digital_IOSignal terminal PA10/R6/T7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10/R6/T7. Supported peripheral buses: General.
18PA11/R7/T6Digital_IOSignal terminal PA11/R7/T6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11/R7/T6. Supported peripheral buses: General.
19NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
20PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, I2C.
21epGNDBottom exposed die attach pad (ep) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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