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CH32V317WCU6 (QFN-68(8x8)mm) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32V317WCU6

WCHID: C49188393QFN-68(8x8)mm · 69 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32V317WCU6 (QFN-68(8x8)mm)1VBAT2PC13/TAMPER-3PC14/OSC32IN4PC15/OSC32OU5OSC_IN/PD06OSC_OUT/PD17NRST8PC0/ADC109PC1/ADC1110PC2/ADC1211PC3/ADC1312VSSA13VDDA14PA0/WKUP/ADC15PA1/ADC116PA2/ADC217PA3/ADC318VIO_419PA4/ADC4/DAC20PA5/ADC5/DAC21PA6/ADC622PA7/ADC723PC4/ADC1424PC5/ADC1525PB0/ADC826PB1/ADC927PB2/BOOT128LED029LED130VDDK31MDITP32MDITN33MDIRP34MDIRN35VDD_ETH69VSS68VDD_367VIO_366PE065PB964PB863BOOT062PB7/USB2DP61PB6/USB2DM60PB559PB458PB357PD256PC1255PC1154PC1053PA1552PA14/SWCLK51VIO_250VDD_249VSS_248PA13/SWDIO47PA12/USB1DP46PA11/USB1DM45PA1044PA943PA842PB10/PD1541PB11/PD1440PB1539PB1438PB1337PB1236VIO_1Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.850.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869E=8.00mm · Pitch e=0.40mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (69/69)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
2PC13/TAMPER-RTCI/OMultiplexed I/O & Peripheral Pin PC13/TAMPER-RTC (RTC/CLK)
3PC14/OSC32INI/OMultiplexed I/O & Peripheral Pin PC14/OSC32IN (RTC/CLK)
4PC15/OSC32OUTI/OMultiplexed I/O & Peripheral Pin PC15/OSC32OUT (RTC/CLK)
5OSC_IN/PD0I/OMultiplexed I/O & Peripheral Pin OSC_IN/PD0 (RTC/CLK)
6OSC_OUT/PD1I/OMultiplexed I/O & Peripheral Pin OSC_OUT/PD1 (RTC/CLK)
7NRSTISystem Enable & Hardware Reset (NRST)
8PC0/ADC10I/OMultiplexed I/O & Peripheral Pin PC0/ADC10 (ADC)
9PC1/ADC11I/OMultiplexed I/O & Peripheral Pin PC1/ADC11 (ADC)
10PC2/ADC12I/OMultiplexed I/O & Peripheral Pin PC2/ADC12 (ADC)
11PC3/ADC13I/OMultiplexed I/O & Peripheral Pin PC3/ADC13 (ADC)
12VSSAGNDGround Reference Pin (VSSA)
13VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
14PA0/WKUP/ADC0I/OMultiplexed I/O & Peripheral Pin PA0/WKUP/ADC0 (ADC)
15PA1/ADC1I/OMultiplexed I/O & Peripheral Pin PA1/ADC1 (ADC)
16PA2/ADC2I/OMultiplexed I/O & Peripheral Pin PA2/ADC2 (ADC)
17PA3/ADC3I/OMultiplexed I/O & Peripheral Pin PA3/ADC3 (ADC)
18VIO_4I/OMultiplexed I/O & Peripheral Pin VIO_4 (General)
19PA4/ADC4/DAC0I/OMultiplexed I/O & Peripheral Pin PA4/ADC4/DAC0 (ADC, DAC)
20PA5/ADC5/DAC1I/OMultiplexed I/O & Peripheral Pin PA5/ADC5/DAC1 (ADC, DAC)
21PA6/ADC6I/OMultiplexed I/O & Peripheral Pin PA6/ADC6 (ADC)
22PA7/ADC7I/OMultiplexed I/O & Peripheral Pin PA7/ADC7 (ADC)
23PC4/ADC14I/OMultiplexed I/O & Peripheral Pin PC4/ADC14 (ADC)
24PC5/ADC15I/OMultiplexed I/O & Peripheral Pin PC5/ADC15 (ADC)
25PB0/ADC8I/OMultiplexed I/O & Peripheral Pin PB0/ADC8 (ADC)
26PB1/ADC9I/OMultiplexed I/O & Peripheral Pin PB1/ADC9 (ADC)
27PB2/BOOT1I/OMultiplexed I/O & Peripheral Pin PB2/BOOT1 (General)
28LED0I/OMultiplexed I/O & Peripheral Pin LED0 (General)
29LED1I/OMultiplexed I/O & Peripheral Pin LED1 (General)
30VDDKPowerPower Supply Input (VDDK — 3.3V / 5.0V Standard Logic)
31MDITPI/OMultiplexed I/O & Peripheral Pin MDITP (General)
32MDITNI/OMultiplexed I/O & Peripheral Pin MDITN (General)
33MDIRPI/OMultiplexed I/O & Peripheral Pin MDIRP (General)
34MDIRNI/OMultiplexed I/O & Peripheral Pin MDIRN (General)
35VDD_ETHPowerPower Supply Input (VDD_ETH — 3.3V / 5.0V Standard Logic)
36VIO_1I/OMultiplexed I/O & Peripheral Pin VIO_1 (General)
37PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
38PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
39PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
40PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
41PB11/PD14I/OMultiplexed I/O & Peripheral Pin PB11/PD14 (General)
42PB10/PD15I/OMultiplexed I/O & Peripheral Pin PB10/PD15 (General)
43PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
44PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
45PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
46PA11/USB1DMI/OMultiplexed I/O & Peripheral Pin PA11/USB1DM (USB)
47PA12/USB1DPI/OMultiplexed I/O & Peripheral Pin PA12/USB1DP (USB)
48PA13/SWDIOI/OMultiplexed I/O & Peripheral Pin PA13/SWDIO (SWD/JTAG)
49VSS_2GNDExposed Thermal & Ground Pad (VSS_2)
50VDD_2PowerPower Supply Input (VDD_2 — 3.3V / 5.0V Standard Logic)
51VIO_2I/OMultiplexed I/O & Peripheral Pin VIO_2 (General)
52PA14/SWCLKI/OMultiplexed I/O & Peripheral Pin PA14/SWCLK (SWD/JTAG)
53PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
54PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
55PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
56PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
57PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
58PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
59PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
60PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
61PB6/USB2DMI/OMultiplexed I/O & Peripheral Pin PB6/USB2DM (USB)
62PB7/USB2DPI/OMultiplexed I/O & Peripheral Pin PB7/USB2DP (USB)
63BOOT0IInput-Only Pin BOOT0 (General)
64PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
65PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
66PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
67VIO_3I/OMultiplexed I/O & Peripheral Pin VIO_3 (General)
68VDD_3PowerPower Supply Input (VDD_3 — 3.3V / 5.0V Standard Logic)
69VSSGNDGround Reference Pin (VSS)
PIN 1 VBAT
Power
Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32V317WCU6 (WCH · QFN-68(8x8)mm)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32V317WCU6 (QFN-68(8x8)mm) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32V317WCU6 (QFN-68(8x8)mm) - 2. Standard Pinout (Top View)
True package pinout (69 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32V317WCU6 (QFN-68(8x8)mm) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32V317WCU6 (QFN-68(8x8)mm) - 4. Package Dimensions (D×E×A)
QFN-68(8x8)mm · 8.00×8.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32V317WCU6 (QFN-68(8x8)mm) - 5. Recommended Land Pattern
IPC-7351B Footprint (69 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32V317WCU6 (QFN-68(8x8)mm) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH32V208 / CH32V305 / CH32V307
P6 · p06_fig01EXACT PACKAGE
CH32V317WCU6 (QFN-68(8x8)mm) — CH32V303/305/307/317 数据手册 https://wch.cn
CH32V303/305/307/317 数据手册 https://wch.cn
P35 · p35_fig02EXACT PACKAGE
CH32V317WCU6 (QFN-68(8x8)mm) — V3.9 34
V3.9 34
P36 · p36_fig01EXACT PACKAGE
CH32V317WCU6 (QFN-68(8x8)mm) — V3.9 35
V3.9 35
P5 · p05_fig011226×1550px
CH32V317WCU6 (QFN-68(8x8)mm) — V3.9 4
V3.9 4
P20 · p20_fig011472×899px
CH32V317WCU6 (QFN-68(8x8)mm) — PA14/SWCLK 49 PA15 50 PC10 51 PC11 52 PC12 53 PD2 54 PB3 55 PB4 56 PB5 57 PB6/USB2DM 58 PB7/USB2DP 59 BOOT0 60 PB8 61 PB9 62 VSS_3 63 VIO_3 64
PA14/SWCLK 49 PA15 50 PC10 51 PC11 52 PC12 53 PD2 54 PB3 55 PB4 56 PB5 57 PB6/USB2DM 58 PB7/USB2DP 59 BOOT0 60 PB8 61 PB9 62 VSS_3 63 VIO_3 64
P20 · p20_fig01P20
CH32V317WCU6 (QFN-68(8x8)mm) — Datasheet Page 20 (p20_fig01)
Datasheet Page 20 (p20_fig01)
P35 · p35_fig011776×925px
CH32V317WCU6 (QFN-68(8x8)mm) — 寄存器相应位配置为11b。 注14：TIM2_CH1 和TIM2_ETR 共用一个引脚，但不能同时使用。 注15、注16：对于CH32V305FBP6芯片，PA5和PA1引脚在芯片内部短接合封，禁止将两个IO均配置为输出
寄存器相应位配置为11b。 注14：TIM2_CH1 和TIM2_ETR 共用一个引脚，但不能同时使用。 注15、注16：对于CH32V305FBP6芯片，PA5和PA1引脚在芯片内部短接合封，禁止将两个IO均配置为输出
P35 · p35_fig02P35
CH32V317WCU6 (QFN-68(8x8)mm) — Datasheet Page 35 (p35_fig02)
Datasheet Page 35 (p35_fig02)

Technical Specifications & Part Details (CH32V317WCU6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:CH32V317WCU6 (QFN-68(8x8)mm) is a 68-pin embedded microcontroller unit (mcu) featuring a 8.00 × 8.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
25MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-68(8x8)mm)
Pin Count & Lead PitchN / e
68 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2/BOOT1, BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol69 auto-grouped pins
OK
IPC-7351B Land Pattern69 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 6.20×6.20mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-68(8x8)mm)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.80 mm
Pins / Total PadsTopology
69P / 69Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-68(8x8)mm
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32V317WCU6 (QFN-68(8x8)mm)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32V317WCU6 (QFN-68(8x8)mm)?

Manufactured by WCH, the CH32V317WCU6 is housed in a QFN-68(8x8)mm package with 69 pins and a 0.40 mm lead pitch. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)), 2 (PC13/TAMPER-RTC: Multiplexed I/O & Peripheral Pin PC13/TAMPER-RTC (RTC/CLK)), 3 (PC14/OSC32IN: Multiplexed I/O & Peripheral Pin PC14/OSC32IN (RTC/CLK)), 4 (PC15/OSC32OUT: Multiplexed I/O & Peripheral Pin PC15/OSC32OUT (RTC/CLK)), 5 (OSC_IN/PD0: Multiplexed I/O & Peripheral Pin OSC_IN/PD0 (RTC/CLK)), 6 (OSC_OUT/PD1: Multiplexed I/O & Peripheral Pin OSC_OUT/PD1 (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for CH32V317WCU6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32V317WCU6 (QFN-68(8x8)mm) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.40 mm, and 69 copper pads plus a central exposed thermal pad (EPAD) of 6.20 × 6.20 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32V317WCU6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32V317WCU6 (WCH, QFN-68(8x8)mm) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (69 pins) & CH32V208 / CH32V305 / CH32V307 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2PC13/TAMPER-RTCDigital_IOSignal terminal PC13/TAMPER-RTC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13/TAMPER-RTC. Supported peripheral buses: RTC/CLK.
3PC14/OSC32INDigital_IOSignal terminal PC14/OSC32IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14/OSC32IN. Supported peripheral buses: RTC/CLK.
4PC15/OSC32OUTDigital_IOSignal terminal PC15/OSC32OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC15/OSC32OUT. Supported peripheral buses: RTC/CLK.
5OSC_IN/PD0Digital_IOSignal terminal OSC_IN/PD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_IN/PD0. Supported peripheral buses: RTC/CLK.
6OSC_OUT/PD1Digital_IOSignal terminal OSC_OUT/PD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_OUT/PD1. Supported peripheral buses: RTC/CLK.
7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8PC0/ADC10AnalogSignal terminal PC0/ADC10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0/ADC10. Supported peripheral buses: ADC.
9PC1/ADC11AnalogSignal terminal PC1/ADC11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1/ADC11. Supported peripheral buses: ADC.
10PC2/ADC12AnalogSignal terminal PC2/ADC12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2/ADC12. Supported peripheral buses: ADC.
11PC3/ADC13AnalogSignal terminal PC3/ADC13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3/ADC13. Supported peripheral buses: ADC.
12VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
13VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
14PA0/WKUP/ADC0AnalogSignal terminal PA0/WKUP/ADC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0/WKUP/ADC0. Supported peripheral buses: ADC.
15PA1/ADC1AnalogSignal terminal PA1/ADC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1/ADC1. Supported peripheral buses: ADC.
16PA2/ADC2AnalogSignal terminal PA2/ADC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2/ADC2. Supported peripheral buses: ADC.
17PA3/ADC3AnalogSignal terminal PA3/ADC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3/ADC3. Supported peripheral buses: ADC.
18VIO_4Digital_IOSignal terminal VIO_4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO_4. Supported peripheral buses: General.
19PA4/ADC4/DAC0AnalogSignal terminal PA4/ADC4/DAC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4/ADC4/DAC0. Supported peripheral buses: ADC, DAC.
20PA5/ADC5/DAC1AnalogSignal terminal PA5/ADC5/DAC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5/ADC5/DAC1. Supported peripheral buses: ADC, DAC.
21PA6/ADC6AnalogSignal terminal PA6/ADC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6/ADC6. Supported peripheral buses: ADC.
22PA7/ADC7AnalogSignal terminal PA7/ADC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7/ADC7. Supported peripheral buses: ADC.
23PC4/ADC14AnalogSignal terminal PC4/ADC14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4/ADC14. Supported peripheral buses: ADC.
24PC5/ADC15AnalogSignal terminal PC5/ADC15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5/ADC15. Supported peripheral buses: ADC.
25PB0/ADC8AnalogSignal terminal PB0/ADC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0/ADC8. Supported peripheral buses: ADC.
26PB1/ADC9AnalogSignal terminal PB1/ADC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1/ADC9. Supported peripheral buses: ADC.
27PB2/BOOT1Digital_IOSignal terminal PB2/BOOT1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2/BOOT1. Supported peripheral buses: General.
28LED0Digital_IOSignal terminal LED0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED0. Supported peripheral buses: General.
29LED1Digital_IOSignal terminal LED1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED1. Supported peripheral buses: General.
30VDDKPower_InPrimary positive power supply input (VDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
31MDITPDigital_IOSignal terminal MDITP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITP. Supported peripheral buses: General.
32MDITNDigital_IOSignal terminal MDITN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITN. Supported peripheral buses: General.
33MDIRPDigital_IOSignal terminal MDIRP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRP. Supported peripheral buses: General.
34MDIRNDigital_IOSignal terminal MDIRN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRN. Supported peripheral buses: General.
35VDD_ETHPower_InPrimary positive power supply input (VDD_ETH) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
36VIO_1Digital_IOSignal terminal VIO_1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO_1. Supported peripheral buses: General.
37PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
38PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
39PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
40PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
41PB11/PD14Digital_IOSignal terminal PB11/PD14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11/PD14. Supported peripheral buses: General.
42PB10/PD15Digital_IOSignal terminal PB10/PD15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10/PD15. Supported peripheral buses: General.
43PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
44PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
45PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
46PA11/USB1DMDigital_IOSignal terminal PA11/USB1DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11/USB1DM. Supported peripheral buses: USB.
47PA12/USB1DPDigital_IOSignal terminal PA12/USB1DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12/USB1DP. Supported peripheral buses: USB.
48PA13/SWDIODigital_IOSignal terminal PA13/SWDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13/SWDIO. Supported peripheral buses: SWD/JTAG.
49VSS_2GNDBottom exposed die attach pad (VSS_2) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
50VDD_2Power_InPrimary positive power supply input (VDD_2) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
51VIO_2Digital_IOSignal terminal VIO_2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO_2. Supported peripheral buses: General.
52PA14/SWCLKDigital_IOSignal terminal PA14/SWCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14/SWCLK. Supported peripheral buses: SWD/JTAG.
53PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
54PC10Digital_IOSignal terminal PC10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
55PC11Digital_IOSignal terminal PC11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
56PC12Digital_IOSignal terminal PC12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
57PD2Digital_IOSignal terminal PD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
58PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
59PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
60PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
61PB6/USB2DMDigital_IOSignal terminal PB6/USB2DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6/USB2DM. Supported peripheral buses: USB.
62PB7/USB2DPDigital_IOSignal terminal PB7/USB2DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7/USB2DP. Supported peripheral buses: USB.
63BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
64PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
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