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CH346C (QFN-26(3x3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH346C

WCHID: C48982391QFN-26(3x3) · 26 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH346C (QFN-26(3x3))1IO12VDD53GND4VDD335XI6XO7VDDK8UD-9UD+10RESET11RDNE12RI1/TNOW1/ G13DCD1/SUSP/ G26DTR1/CFG1/ G25D5/SCK/CTS1/24DSR1/GPIO1123D3/SPI_WRNF/22RXD121TXD020RXD019CTS0/ GPIO118RTS0/ GPIO017DSR0/ACT/16DTR0/RX S/_ 15CS14VIOGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.222.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
1245678910111213141516171819202122232425263E=3.00mm · Pitch e=0.40mmD=3.00mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 3.00mm × 3.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (26/26)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1IO1I/OGeneral Purpose Digital I/O Pin IO1
2VDD5PowerPower Supply Input (VDD5 — 1.2V to 3.3V)
3GNDGNDGround Reference Pin (GND)
4VDD33PowerPower Supply Input (VDD33 — 1.2V to 3.3V)
5XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
6XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
7VDDKPowerPower Supply Input (VDDK — 1.2V to 3.3V)
8UD-I/OMultiplexed I/O & Peripheral Pin UD- (USB)
9UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
10RESETISystem Enable & Hardware Reset (RESET)
11RDNEI/OMultiplexed I/O & Peripheral Pin RDNE (General)
12RI1/TNOW1/ GPIO6I/OMultiplexed I/O & Peripheral Pin RI1/TNOW1/ GPIO6 (UART)
13DCD1/SUSP/ GPIO7I/OMultiplexed I/O & Peripheral Pin DCD1/SUSP/ GPIO7 (USB, UART)
14VIOI/OMultiplexed I/O & Peripheral Pin VIO (General)
15CSI/OMultiplexed I/O & Peripheral Pin CS (General)
16DTR0/RX S/_ GPIO2/CFG0I/OMultiplexed I/O & Peripheral Pin DTR0/RX S/_ GPIO2/CFG0 (UART)
17DSR0/ACT/I/OMultiplexed I/O & Peripheral Pin DSR0/ACT/ (UART)
18RTS0/ GPIO0I/OMultiplexed I/O & Peripheral Pin RTS0/ GPIO0 (UART)
19CTS0/ GPIO1I/OMultiplexed I/O & Peripheral Pin CTS0/ GPIO1 (UART)
20RXD0I/OMultiplexed I/O & Peripheral Pin RXD0 (UART)
21TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
22RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
23D3/SPI_WRNF/TXD1I/OMultiplexed I/O & Peripheral Pin D3/SPI_WRNF/TXD1 (UART, SPI)
24DSR1/GPIO11I/OMultiplexed I/O & Peripheral Pin DSR1/GPIO11 (UART)
25D5/SCK/CTS1/GPIO9I/OMultiplexed I/O & Peripheral Pin D5/SCK/CTS1/GPIO9 (UART, SPI)
26DTR1/CFG1/ GPIO10I/OMultiplexed I/O & Peripheral Pin DTR1/CFG1/ GPIO10 (UART)
PIN 1 IO1
I/O
General Purpose Digital I/O Pin IO1
Design note: 3.3V logic domain (3.6V absolute max), 40mA max drive current.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH346C (WCH · QFN-26(3x3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH346C (QFN-26(3x3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH346C (QFN-26(3x3)) - 2. Standard Pinout (Top View)
True package pinout (26 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH346C (QFN-26(3x3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH346C (QFN-26(3x3)) - 4. Package Dimensions (D×E×A)
QFN-26(3x3) · 3.00×3.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH346C (QFN-26(3x3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (26 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH346C (QFN-26(3x3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for CH346
P1 · p01_fig011468×528px
CH346C (QFN-26(3x3)) — 图1-1 系统框图
图1-1 系统框图
P2 · p02_fig011697×1271px
CH346C (QFN-26(3x3)) — V1.1 2
V1.1 2
P2 · p02_fig01P2
CH346C (QFN-26(3x3)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P4 · p04_fig011620×1051px
CH346C (QFN-26(3x3)) — 引脚号 引脚名称 类型 引脚说明
引脚号 引脚名称 类型 引脚说明
P15 · p15_fig012037×2456px
CH346C (QFN-26(3x3)) — 图8-1 高速USB 转被动并口参考电路图
图8-1 高速USB 转被动并口参考电路图
P17 · p17_fig012051×2331px
CH346C (QFN-26(3x3)) — 图8-2 高速USB 转被动SPI 接口及串口参考电路图
图8-2 高速USB 转被动SPI 接口及串口参考电路图
P18 · p18_fig011957×2230px
CH346C (QFN-26(3x3)) — 图8-3 高速USB 转双串口参考电路图
图8-3 高速USB 转双串口参考电路图

Technical Specifications & Part Details (CH346C)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH346C (QFN-26(3x3)) is a 26-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.90 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.2V to 3.3V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.2V to 3.3V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-26(3x3))
Pin Count & Lead PitchN / e
26 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol26 auto-grouped pins
OK
IPC-7351B Land Pattern26 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 2.10×2.75mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-26(3x3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.40 mm
Pins / Total PadsTopology
26P / 26Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-26(3x3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH346C (QFN-26(3x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH346C (QFN-26(3x3))?

Manufactured by WCH, the CH346C is housed in a QFN-26(3x3) package with 26 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.2V to 3.3V. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (VDD5: Power Supply Input (VDD5 — 1.2V to 3.3V)), 3 (GND: Ground Reference Pin (GND)), 4 (VDD33: Power Supply Input (VDD33 — 1.2V to 3.3V)), 5 (XI: Multiplexed I/O & Peripheral Pin XI (RTC/CLK)), 6 (XO: Multiplexed I/O & Peripheral Pin XO (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for CH346C?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH346C (QFN-26(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.40 mm, and 26 copper pads plus a central exposed thermal pad (EPAD) of 2.10 × 2.75 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH346C?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH346C (WCH, QFN-26(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (26 pins) & CH346 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1IO1Digital_IOGeneral Purpose Digital I/O Pin IO1
2VDD5Power_InPrimary positive power supply input (VDD5) operating in the 1.2V to 3.3V domain (Max rating: 3.3V).
3GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
4VDD33Power_InPrimary positive power supply input (VDD33) operating in the 1.2V to 3.3V domain (Max rating: 3.3V).
5XIDigital_IOSignal terminal XI (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
6XODigital_IOSignal terminal XO (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
7VDDKPower_InPrimary positive power supply input (VDDK) operating in the 1.2V to 3.3V domain (Max rating: 3.3V).
8UD-Digital_IOSignal terminal UD- (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB.
9UD+Digital_IOSignal terminal UD+ (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
10RESETDigital_IOActive-low hardware reset terminal (RESET): pulling this pin Low resets the processor core and peripherals.
11RDNEDigital_IOSignal terminal RDNE (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: RDNE. Supported peripheral buses: General.
12RI1/TNOW1/ GPIO6Digital_IOSignal terminal RI1/TNOW1/ GPIO6 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: RI1/TNOW1/ GPIO6. Supported peripheral buses: UART.
13DCD1/SUSP/ GPIO7Digital_IOSignal terminal DCD1/SUSP/ GPIO7 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: DCD1/SUSP/ GPIO7. Supported peripheral buses: USB, UART.
14VIODigital_IOSignal terminal VIO (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: VIO. Supported peripheral buses: General.
15CSDigital_IOSignal terminal CS (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: CS. Supported peripheral buses: General.
16DTR0/RX S/_ GPIO2/CFG0Digital_IOSignal terminal DTR0/RX S/_ GPIO2/CFG0 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: DTR0/RX S/_ GPIO2/CFG0. Supported peripheral buses: UART.
17DSR0/ACT/Digital_IOSignal terminal DSR0/ACT/ (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: DSR0/ACT/. Supported peripheral buses: UART.
18RTS0/ GPIO0Digital_IOSignal terminal RTS0/ GPIO0 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: RTS0/ GPIO0. Supported peripheral buses: UART.
19CTS0/ GPIO1Digital_IOSignal terminal CTS0/ GPIO1 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: CTS0/ GPIO1. Supported peripheral buses: UART.
20RXD0Digital_IOSignal terminal RXD0 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: RXD0. Supported peripheral buses: UART.
21TXD0Digital_IOSignal terminal TXD0 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
22RXD1Digital_IOSignal terminal RXD1 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART.
23D3/SPI_WRNF/TXD1Digital_IOSignal terminal D3/SPI_WRNF/TXD1 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: SPI_WRNF, SPI. Supported peripheral buses: UART, SPI.
24DSR1/GPIO11Digital_IOSignal terminal DSR1/GPIO11 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: DSR1/GPIO11. Supported peripheral buses: UART.
25D5/SCK/CTS1/GPIO9Digital_IOSignal terminal D5/SCK/CTS1/GPIO9 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: GPIO9, SPI. Supported peripheral buses: UART, SPI.
26DTR1/CFG1/ GPIO10Digital_IOSignal terminal DTR1/CFG1/ GPIO10 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: DTR1/CFG1/ GPIO10. Supported peripheral buses: UART.
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