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CH579F (QFN-28-EP(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH579F

WCHID: C481975QFN-28-EP(4x4) · 29 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH579F (QFN-28-EP(4x4))1PA11/X32KO/T2PA10/X32KI/T3VDCID4VSW5VIO336PA87PA98PB89PB1710PB1611PB1512PB1413PB1314PB1215PB1129EP28PA12/SCS/AIN27PA13/SCK0/AI26IO2125PB2324PB023PB122PB221PB320PB419PB518PB617PB716PB10Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.225.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829E=4.00mm · Pitch e=0.50mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PA11/X32KO/TMR2I/OMultiplexed I/O & Peripheral Pin PA11/X32KO/TMR2 (General)
2PA10/X32KI/TMR1I/OMultiplexed I/O & Peripheral Pin PA10/X32KI/TMR1 (General)
3VDCIDI/OMultiplexed I/O & Peripheral Pin VDCID (General)
4VSWI/OMultiplexed I/O & Peripheral Pin VSW (General)
5VIO33I/OMultiplexed I/O & Peripheral Pin VIO33 (General)
6PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
7PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
8PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
9PB17I/OMultiplexed I/O & Peripheral Pin PB17 (General)
10PB16I/OMultiplexed I/O & Peripheral Pin PB16 (General)
11PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
12PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
13PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
14PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
15PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
16PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
17PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
18PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
19PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
20PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
21PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
22PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
23PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
24PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
25PB23I/OMultiplexed I/O & Peripheral Pin PB23 (General)
26IO21I/OGPIO21 / RTC_GPIO21
27PA13/SCK0/AIN3I/OMultiplexed I/O & Peripheral Pin PA13/SCK0/AIN3 (SPI, ADC)
28PA12/SCS/AIN2I/OMultiplexed I/O & Peripheral Pin PA12/SCS/AIN2 (ADC)
29EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 PA11/X32KO/TMR2
I/O
Multiplexed I/O & Peripheral Pin PA11/X32KO/TMR2 (General)
Design note: Signal terminal PA11/X32KO/TMR2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11/X32KO/TMR2. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH579F (WCH · QFN-28-EP(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH579F (QFN-28-EP(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH579F (QFN-28-EP(4x4)) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH579F (QFN-28-EP(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH579F (QFN-28-EP(4x4)) - 4. Package Dimensions (D×E×A)
QFN-28-EP(4x4) · 4.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH579F (QFN-28-EP(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH579F (QFN-28-EP(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for CH579
P3 · p03_fig01EXACT PACKAGE
CH579F (QFN-28-EP(4x4)) — Figure 1-1 Pin configuration of CH579M (QFN48_5X5) and CH579F (QFN28_4X4) package
Figure 1-1 Pin configuration of CH579M (QFN48_5X5) and CH579F (QFN28_4X4) package
P109 · p109_fig01EXACT PACKAGE
CH579F (QFN-28-EP(4x4)) — Note: The unit of dimensions indicated is mm. The distance between centers of the pins is equal to the nominal value. The dimensional error other than this is not more than ±0.2mm. QFN28 | QFN48
Note: The unit of dimensions indicated is mm. The distance between centers of the pins is equal to the nominal value. The dimensional error other than this is not more than ±0.2mm. QFN28 | QFN48
P1 · p01_fig01304×162px
CH579F (QFN-28-EP(4x4)) — PDF Figure p01_fig01 (Page 1 — LOGO_OR_NOISE)
PDF Figure p01_fig01 (Page 1 — LOGO_OR_NOISE)
P3 · p03_fig01P3
CH579F (QFN-28-EP(4x4)) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P109 · p109_fig02All Packages in PDF
CH579F (QFN-28-EP(4x4)) — QFN48
QFN48

Technical Specifications & Part Details (CH579F)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH579F (QFN-28-EP(4x4)) is a 28-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, UART, SPI, ADC, PWM interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
40MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-28-EP(4x4))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, UART, SPI, ADC, PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 2.80×2.80mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-28-EP(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-28-EP(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH579F (QFN-28-EP(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH579F (QFN-28-EP(4x4))?

Manufactured by WCH, the CH579F is housed in a QFN-28-EP(4x4) package with 29 pins and a 0.50 mm lead pitch. Key pins include: 1 (PA11/X32KO/TMR2: Multiplexed I/O & Peripheral Pin PA11/X32KO/TMR2 (General)), 2 (PA10/X32KI/TMR1: Multiplexed I/O & Peripheral Pin PA10/X32KI/TMR1 (General)), 3 (VDCID: Multiplexed I/O & Peripheral Pin VDCID (General)), 4 (VSW: Multiplexed I/O & Peripheral Pin VSW (General)), 5 (VIO33: Multiplexed I/O & Peripheral Pin VIO33 (General)), 6 (PA8: Multiplexed I/O & Peripheral Pin PA8 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH579F?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH579F (QFN-28-EP(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 2.80 × 2.80 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH579F?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH579F (WCH, QFN-28-EP(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & CH579 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PA11/X32KO/TMR2Digital_IOSignal terminal PA11/X32KO/TMR2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11/X32KO/TMR2. Supported peripheral buses: General.
2PA10/X32KI/TMR1Digital_IOSignal terminal PA10/X32KI/TMR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10/X32KI/TMR1. Supported peripheral buses: General.
3VDCIDDigital_IOSignal terminal VDCID (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VDCID. Supported peripheral buses: General.
4VSWDigital_IOSignal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: General.
5VIO33Digital_IOSignal terminal VIO33 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO33. Supported peripheral buses: General.
6PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
7PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
8PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
9PB17Digital_IOSignal terminal PB17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB17. Supported peripheral buses: General.
10PB16Digital_IOSignal terminal PB16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB16. Supported peripheral buses: General.
11PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
12PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
13PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
14PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
15PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
16PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
17PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
18PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
19PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
20PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
21PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
22PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
23PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
24PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
25PB23Digital_IOSignal terminal PB23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB23. Supported peripheral buses: General.
26IO21Digital_IOGPIO21 / RTC_GPIO21
27PA13/SCK0/AIN3Digital_IOSignal terminal PA13/SCK0/AIN3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI, ADC.
28PA12/SCS/AIN2AnalogSignal terminal PA12/SCS/AIN2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12/SCS/AIN2. Supported peripheral buses: ADC.
29EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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