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C473010 (WIFIM-SMD_20P-L16.0-W23.0-P1.50) — Symbol, Footprint IPC-7351B & 3D STEP Model

C473010

SemiconductorWIFIM-SMD_20P-L16.0-W23.0-P1.50 · 21 Pins · Pitch 1.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C473010 (WIFIM-SMD_20P-L16.0-W23.0-P1.50)1GND23V33IO164IO155IO26IO07IO48SD2/IO99SD3/CS10CMD/MOSI11GND21GND20EN19ADC_IN18RST17IO516TXD15RXD14SD1/INT13SD0/MISO12SCLKGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.220.315.210.25.10-5.1-10.2-15.2-20.3mm
2. 2D FOOTPRINT
ANTENNA KEEPOUT (7.0mm)123456789101112131415161718192021E=16.00mm · Pitch e=1.50mmD=23.00mm-14-12-10-8-6-4-2024681012141715131197531-1-3-5-7-9-11-13-15-17mm
3. 3D CAD MODEL
Package Body: 16.00mm × 23.00mm · Pitch: 1.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (21/21)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1GNDGNDGround Reference Pin (GND)
23V3PowerPower Supply Input (3V3 — 3.3V / 5.0V Standard Logic)
3IO16I/OMultiplexed I/O & Peripheral Pin IO16 (General)
4IO15I/OMultiplexed I/O & Peripheral Pin IO15 (General)
5IO2I/OMultiplexed I/O & Peripheral Pin IO2 (General)
6IO0I/OMultiplexed I/O & Peripheral Pin IO0 (General)
7IO4I/OMultiplexed I/O & Peripheral Pin IO4 (General)
8SD2/IO9I/OMultiplexed I/O & Peripheral Pin SD2/IO9 (General)
9SD3/CSI/OMultiplexed I/O & Peripheral Pin SD3/CS (General)
10CMD/MOSII/OMultiplexed I/O & Peripheral Pin CMD/MOSI (SPI)
11GNDGNDGround Reference Pin (GND)
12SCLKI/OMultiplexed I/O & Peripheral Pin SCLK (SPI, I2C)
13SD0/MISOI/OMultiplexed I/O & Peripheral Pin SD0/MISO (SPI)
14SD1/INTI/OMultiplexed I/O & Peripheral Pin SD1/INT (General)
15RXDI/OMultiplexed I/O & Peripheral Pin RXD (UART)
16TXDI/OMultiplexed I/O & Peripheral Pin TXD (UART)
17IO5I/OMultiplexed I/O & Peripheral Pin IO5 (General)
18RSTI/OMultiplexed I/O & Peripheral Pin RST (General)
19ADC_INI/OMultiplexed I/O & Peripheral Pin ADC_IN (ADC)
20ENISystem Enable & Hardware Reset (EN)
21GNDGNDGround Reference Pin (GND)
PIN 1 GND
GND
Ground Reference Pin (GND)
Design note: 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C473010 (Semiconductor · WIFIM-SMD_20P-L16.0-W23.0-P1.50)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C473010 (WIFIM-SMD_20P-L16.0-W23.0-P1.50) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C473010 (WIFIM-SMD_20P-L16.0-W23.0-P1.50) - 2. Standard Pinout (Top View)
True package pinout (21 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C473010 (WIFIM-SMD_20P-L16.0-W23.0-P1.50) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C473010 (WIFIM-SMD_20P-L16.0-W23.0-P1.50) - 4. Package Dimensions (D×E×A)
WIFIM-SMD_20P-L16.0-W23.0-P1.50 · 16.00×23.00mm · Pitch 1.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
C473010 (WIFIM-SMD_20P-L16.0-W23.0-P1.50) - 5. Recommended Land Pattern
IPC-7351B Footprint (21 Pads)Expand ›
6. Application SchematicSCHEMATIC
C473010 (WIFIM-SMD_20P-L16.0-W23.0-P1.50) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C473010)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Wireless Wi-Fi / Bluetooth LE SoC Module
Detailed Overview:C473010 (WIFIM-SMD_20P-L16.0-W23.0-P1.50) is a 20-pin wireless wi-fi / bluetooth le soc module featuring a 23.25 × 17.10 × 3.10 mm mechanical envelope (lead pitch e = 1.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated ADC, I2C, SPI, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
23.25 × 17.10 × 3.10 mm (A1=0.00 mm)
Package family: CASTELLATED_MODULE (WIFIM-SMD_20P-L16.0-W23.0-P1.50)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 1.50 mm (59.1 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
ADC, I2C, SPI, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol21 auto-grouped pins
OK
IPC-7351B Land Pattern21 pads · Pitch 1.50mm
OK
IPC-7525 60% Solder PasteEPAD 4.50×4.50mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WIFIM-SMD_20P-L16.0-W23.0-P1.50)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
23.00 × 16.00 mm
Height (A) & Pitch (e)IPC-7351B
A=2.40mm · e=1.50mm
Pad Size (W × L)Level B
0.90 × 1.60 mm
Pins / Total PadsTopology
21P / 21Pad (CASTELLATED_MODULE)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WIFIM-SMD_20P-L16.0-W23.0-P1.50
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C473010 (WIFIM-SMD_20P-L16.0-W23.0-P1.50)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C473010 (WIFIM-SMD_20P-L16.0-W23.0-P1.50)?

Manufactured by Semiconductor, the C473010 is housed in a WIFIM-SMD_20P-L16.0-W23.0-P1.50 package with 21 pins and a 1.50 mm lead pitch. Key pins include: 1 (GND: Ground Reference Pin (GND)), 2 (3V3: Power Supply Input (3V3 — 3.3V / 5.0V Standard Logic)), 3 (IO16: Multiplexed I/O & Peripheral Pin IO16 (General)), 4 (IO15: Multiplexed I/O & Peripheral Pin IO15 (General)), 5 (IO2: Multiplexed I/O & Peripheral Pin IO2 (General)), 6 (IO0: Multiplexed I/O & Peripheral Pin IO0 (General)).

What are the IPC-7351B PCB Footprint dimensions for C473010?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C473010 (WIFIM-SMD_20P-L16.0-W23.0-P1.50) has a nominal body envelope of 16.00 × 23.00 mm, pitch e = 1.50 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 4.50 × 4.50 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C473010?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C473010 (Semiconductor, WIFIM-SMD_20P-L16.0-W23.0-P1.50) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (21 pins) & ESP-WROOM Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
23V3Power_InPrimary positive power supply input (3V3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3IO16Digital_IOSignal terminal IO16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO16. Supported peripheral buses: General.
4IO15Digital_IOSignal terminal IO15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO15. Supported peripheral buses: General.
5IO2Digital_IOSignal terminal IO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO2. Supported peripheral buses: General.
6IO0Digital_IOSignal terminal IO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO0. Supported peripheral buses: General.
7IO4Digital_IOSignal terminal IO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO4. Supported peripheral buses: General.
8SD2/IO9Digital_IOSignal terminal SD2/IO9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD2/IO9. Supported peripheral buses: General.
9SD3/CSDigital_IOSignal terminal SD3/CS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD3/CS. Supported peripheral buses: General.
10CMD/MOSIDigital_IOSignal terminal CMD/MOSI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CMD/MOSI. Supported peripheral buses: SPI.
11GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
12SCLKDigital_IOSignal terminal SCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCLK. Supported peripheral buses: SPI, I2C.
13SD0/MISODigital_IOSignal terminal SD0/MISO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD0/MISO. Supported peripheral buses: SPI.
14SD1/INTDigital_IOSignal terminal SD1/INT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD1/INT. Supported peripheral buses: General.
15RXDDigital_IOSignal terminal RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART.
16TXDDigital_IOSignal terminal TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
17IO5Digital_IOSignal terminal IO5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO5. Supported peripheral buses: General.
18RSTDigital_IOSignal terminal RST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST. Supported peripheral buses: General.
19ADC_INDigital_IOSignal terminal ADC_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ADC_IN. Supported peripheral buses: ADC.
20ENDigital_IOChip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset.
21GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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