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PIC16F818-I/SS (SSOP-20) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC16F818-I/SS

MICROCHIPID: C461620SSOP-20 · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC16F818-I/SS (SSOP-20)1RA2/AN2/VREF2RA3/AN3/VREF3RA4/AN4/T0CK4RA5/MCLR/VPP5VSS6RB0/INT7RB1/SDI/SDA8RB2/SDO/CCP19RB3/CCP1/PGM10RB4/SCK/SCL20P2019P1918RA1/AN117RA0/AN016RA7/OSC1/CLK15RA6/OSC2/CLK14VDD13RB7/T1OSI/PG12RB6/T1OSO/T111RB5/SS#Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891020191817161514131211E=6.50mm · Pitch e=0.65mmD=4.40mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 6.50mm × 4.40mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RA2/AN2/VREF-AnalogMultiplexed I/O & Peripheral Pin RA2/AN2/VREF- (General)
2RA3/AN3/VREF+AnalogMultiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)
3RA4/AN4/T0CKII/OMultiplexed I/O & Peripheral Pin RA4/AN4/T0CKI (General)
4RA5/MCLR/VPPI/OMultiplexed I/O & Peripheral Pin RA5/MCLR/VPP (General)
5VSSGNDGround Reference Pin (VSS)
6RB0/INTI/OMultiplexed I/O & Peripheral Pin RB0/INT (General)
7RB1/SDI/SDAI/OMultiplexed I/O & Peripheral Pin RB1/SDI/SDA (I2C)
8RB2/SDO/CCP1I/OMultiplexed I/O & Peripheral Pin RB2/SDO/CCP1 (General)
9RB3/CCP1/PGMI/OMultiplexed I/O & Peripheral Pin RB3/CCP1/PGM (General)
10RB4/SCK/SCLI/OMultiplexed I/O & Peripheral Pin RB4/SCK/SCL (SPI, I2C)
11RB5/SS#I/OMultiplexed I/O & Peripheral Pin RB5/SS# (General)
12RB6/T1OSO/T1CKI/PGCI/OMultiplexed I/O & Peripheral Pin RB6/T1OSO/T1CKI/PGC (General)
13RB7/T1OSI/PGDI/OMultiplexed I/O & Peripheral Pin RB7/T1OSI/PGD (General)
14VDDPowerPower Supply Input (VDD — 2.0V to 5.5V)
15RA6/OSC2/CLKOI/OMultiplexed I/O & Peripheral Pin RA6/OSC2/CLKO (RTC/CLK)
16RA7/OSC1/CLKII/OMultiplexed I/O & Peripheral Pin RA7/OSC1/CLKI (RTC/CLK)
17RA0/AN0I/OMultiplexed I/O & Peripheral Pin RA0/AN0 (General)
18RA1/AN1I/OMultiplexed I/O & Peripheral Pin RA1/AN1 (General)
19P19I/OMultiplexed I/O & Peripheral Pin P19 (General)
20P20I/OMultiplexed I/O & Peripheral Pin P20 (General)
PIN 1 RA2/AN2/VREF-
Analog
Multiplexed I/O & Peripheral Pin RA2/AN2/VREF- (General)
Design note: Signal terminal RA2/AN2/VREF- (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA2/AN2/VREF-. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 16 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC16F818-I/SS (MICROCHIP · SSOP-20)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC16F818-I/SS (SSOP-20) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC16F818-I/SS (SSOP-20) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC16F818-I/SS (SSOP-20) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC16F818-I/SS (SSOP-20) - 4. Package Dimensions (D×E×A)
SSOP-20 · 6.50×4.40mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC16F818-I/SS (SSOP-20) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC16F818-I/SS (SSOP-20) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (16 figures · Page 1/2)
Showing 1–12 of 16 uncropped original figures for PIC16F818
P1 · p01_fig011777×735px
PIC16F818-I/SS (SSOP-20) — 250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, 8 MHz
250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, 8 MHz
P1 · p01_fig021780×468px
PIC16F818-I/SS (SSOP-20) —  2001-2013 Microchip Technology Inc. DS39598F-page 1 | Device | Program Memory Data Memory | I/O Pins 10-bit A/D (ch) | CCP (PWM) | SSP | Timers 8/16-bit Flash (Bytes) | # Single-Word | Instructions | SRAM (Bytes) | EEPROM | (Bytes) SPI Sl
 2001-2013 Microchip Technology Inc. DS39598F-page 1 | Device | Program Memory Data Memory | I/O Pins 10-bit A/D (ch) | CCP (PWM) | SSP | Timers 8/16-bit Flash (Bytes) | # Single-Word | Instructions | SRAM (Bytes) | EEPROM | (Bytes) SPI Sl
P1 · p01_fig01P1
PIC16F818-I/SS (SSOP-20) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P2 · p02_fig02846×447px
PIC16F818-I/SS (SSOP-20) — RA3/AN3/VREF+
RA3/AN3/VREF+
P5 · p05_fig011777×425px
PIC16F818-I/SS (SSOP-20) — PIC16F818/819 | 1.0 DEVICE OVERVIEW | There are 16 I/O pins that are user configurable on a pin-to-pin basis. Some pins are multiplexed with other device functions. These functions include: | PIC16F819 2K x14 256 x 8 256 x 8 | Device Progra
PIC16F818/819 | 1.0 DEVICE OVERVIEW | There are 16 I/O pins that are user configurable on a pin-to-pin basis. Some pins are multiplexed with other device functions. These functions include: | PIC16F819 2K x14 256 x 8 256 x 8 | Device Progra
P5 · p05_fig02868×339px
PIC16F818-I/SS (SSOP-20) — TABLE 1-1: AVAILABLE MEMORY IN PIC16F818/819 DEVICES | Device Program | Flash | Data Memory | Data EEPROM | PIC16F818 1K x 14 128 x 8 128 x 8
TABLE 1-1: AVAILABLE MEMORY IN PIC16F818/819 DEVICES | Device Program | Flash | Data Memory | Data EEPROM | PIC16F818 1K x 14 128 x 8 128 x 8
P5 · p05_fig01P5
PIC16F818-I/SS (SSOP-20) — Datasheet Page 5 (p05_fig01)
Datasheet Page 5 (p05_fig01)
P66 · p66_fig011754×691px
PIC16F818-I/SS (SSOP-20) — Capture Enable
Capture Enable
P66 · p66_fig021753×640px
PIC16F818-I/SS (SSOP-20) — FIGURE 9-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
FIGURE 9-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
P67 · p67_fig011705×684px
PIC16F818-I/SS (SSOP-20) — FIGURE 9-2: COMPARE MODE OPERATION BLOCK DIAGRAM
FIGURE 9-2: COMPARE MODE OPERATION BLOCK DIAGRAM
P101 · p101_fig011778×1287px
PIC16F818-I/SS (SSOP-20) — FIGURE 12-10: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
FIGURE 12-10: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
P102 · p102_fig011778×1400px
PIC16F818-I/SS (SSOP-20) — The following LVP steps assume the LVP bit is set in the Configuration Word register.
The following LVP steps assume the LVP bit is set in the Configuration Word register.
Page 1 / 2 (16 extracted figures)

Technical Specifications & Part Details (PIC16F818-I/SS)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC16F818-I/SS (SSOP-20) is a 20-pin standard electronic & interconnect component featuring a 6.50 × 4.40 × 1.10 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 2.0V to 5.5V supply operation across -10°C to +85°C with integrated SPI, I2C, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
2.0V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-10°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
1 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.50 × 4.40 × 1.10 mm (A1=0.10 mm)
Package family: TSSOP (SSOP-20)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, I2C, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SSOP-20)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.50 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.10mm · e=0.65mm
Pad Size (W × L)Level B
0.40 × 1.35 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SSOP-20
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC16F818-I/SS (SSOP-20)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC16F818-I/SS (SSOP-20)?

Manufactured by MICROCHIP, the PIC16F818-I/SS is housed in a SSOP-20 package with 20 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.0V to 5.5V. Key pins include: 1 (RA2/AN2/VREF-: Multiplexed I/O & Peripheral Pin RA2/AN2/VREF- (General)), 2 (RA3/AN3/VREF+: Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)), 3 (RA4/AN4/T0CKI: Multiplexed I/O & Peripheral Pin RA4/AN4/T0CKI (General)), 4 (RA5/MCLR/VPP: Multiplexed I/O & Peripheral Pin RA5/MCLR/VPP (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (RB0/INT: Multiplexed I/O & Peripheral Pin RB0/INT (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC16F818-I/SS?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16F818-I/SS (SSOP-20) has a nominal body envelope of 4.40 × 6.50 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16F818-I/SS?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16F818-I/SS (MICROCHIP, SSOP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & PIC16F818 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RA2/AN2/VREF-AnalogSignal terminal RA2/AN2/VREF- (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA2/AN2/VREF-. Supported peripheral buses: General.
2RA3/AN3/VREF+AnalogSignal terminal RA3/AN3/VREF+ (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA3/AN3/VREF+. Supported peripheral buses: General.
3RA4/AN4/T0CKIDigital_IOSignal terminal RA4/AN4/T0CKI (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA4/AN4/T0CKI. Supported peripheral buses: General.
4RA5/MCLR/VPPDigital_IOSignal terminal RA5/MCLR/VPP (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA5/MCLR/VPP. Supported peripheral buses: General.
5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
6RB0/INTDigital_IOSignal terminal RB0/INT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB0/INT. Supported peripheral buses: General.
7RB1/SDI/SDADigital_IOSignal terminal RB1/SDI/SDA (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB1/SDI/SDA. Supported peripheral buses: I2C.
8RB2/SDO/CCP1Digital_IOSignal terminal RB2/SDO/CCP1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB2/SDO/CCP1. Supported peripheral buses: General.
9RB3/CCP1/PGMDigital_IOSignal terminal RB3/CCP1/PGM (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB3/CCP1/PGM. Supported peripheral buses: General.
10RB4/SCK/SCLDigital_IOSignal terminal RB4/SCK/SCL (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB4/SCK/SCL. Supported peripheral buses: SPI, I2C.
11RB5/SS#Digital_IOSignal terminal RB5/SS# (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB5/SS#. Supported peripheral buses: General.
12RB6/T1OSO/T1CKI/PGCDigital_IOSignal terminal RB6/T1OSO/T1CKI/PGC (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB6/T1OSO/T1CKI/PGC. Supported peripheral buses: General.
13RB7/T1OSI/PGDDigital_IOSignal terminal RB7/T1OSI/PGD (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB7/T1OSI/PGD. Supported peripheral buses: General.
14VDDPower_InPrimary positive power supply input (VDD) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
15RA6/OSC2/CLKODigital_IOSignal terminal RA6/OSC2/CLKO (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA6/OSC2/CLKO. Supported peripheral buses: RTC/CLK.
16RA7/OSC1/CLKIDigital_IOSignal terminal RA7/OSC1/CLKI (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA7/OSC1/CLKI. Supported peripheral buses: RTC/CLK.
17RA0/AN0Digital_IOSignal terminal RA0/AN0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA0/AN0. Supported peripheral buses: General.
18RA1/AN1Digital_IOSignal terminal RA1/AN1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA1/AN1. Supported peripheral buses: General.
19P19Digital_IOSignal terminal P19 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: P19. Supported peripheral buses: General.
20P20Digital_IOSignal terminal P20 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: P20. Supported peripheral buses: General.
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