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CH634W7V (QFN-76(9x9)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH634W7V

WCHID: C46061836QFN-76(9x9) · 77 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH634W7V (QFN-76(9x9))1NC2P1_SS_TXA3P1_VDD124P1_SS_RXB5P1_SS_RXA6NC7P1_HS_DP8P1_HS_DM9NC10P4_SS_TXB11P4_SS_TXA12P4_VDD1213P4_SS_RXB14P4_SS_RXA15NC16P4_HS_DP17P4_HS_DM18OVCUR2#19PWREN220VDD521VDD3322NC23PWREN_POL24RESET#25OVCUR1#26PWREN127OVCUR4#28PWREN429AVDD3330GPIO331GPIO232LED_A4/SPI_S33LED_A3/SPI_M34LED_A2/SPI_S35LED_A1/SPI_M36SMBCLK/GPIO137NC38VDD539VSW77GND76NC75P2_HS_DM74P2_HS_DP73NC72P2_SS_RXA71P2_SS_RXB70P2_VDD1269P2_SS_TXA68P2_SS_TXB67NC66P3_HS_DM65P3_HS_DP64NC63P3_SS_RXA62P3_SS_RXB61P3_VDD1260P3_SS_TXA59P3_SS_TXB58NC57GND56NC55XO54UP_HS_DM53UP_HS_DP52NC51UP_SS_RXA50UP_SS_RXB49UP_VDD1248UP_SS_TXA47UP_SS_TXB46DVDD1245VBUS_DET44PWRON_DET43VIO3342PWREN341OVCUR3#40VFBGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.255.950.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8-55.9mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677E=9.00mm · Pitch e=0.40mmD=9.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 9.00mm × 9.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (77/77)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1NCI/OMultiplexed I/O & Peripheral Pin NC (General)
2P1_SS_TXAI/OMultiplexed I/O & Peripheral Pin P1_SS_TXA (General)
3P1_VDD12PowerPower Supply Input (P1_VDD12 — 3.3V / 5.0V Standard Logic)
4P1_SS_RXBI/OMultiplexed I/O & Peripheral Pin P1_SS_RXB (General)
5P1_SS_RXAI/OMultiplexed I/O & Peripheral Pin P1_SS_RXA (General)
6NCI/OMultiplexed I/O & Peripheral Pin NC (General)
7P1_HS_DPI/OMultiplexed I/O & Peripheral Pin P1_HS_DP (General)
8P1_HS_DMI/OMultiplexed I/O & Peripheral Pin P1_HS_DM (General)
9NCI/OMultiplexed I/O & Peripheral Pin NC (General)
10P4_SS_TXBI/OMultiplexed I/O & Peripheral Pin P4_SS_TXB (General)
11P4_SS_TXAI/OMultiplexed I/O & Peripheral Pin P4_SS_TXA (General)
12P4_VDD12PowerPower Supply Input (P4_VDD12 — 3.3V / 5.0V Standard Logic)
13P4_SS_RXBI/OMultiplexed I/O & Peripheral Pin P4_SS_RXB (General)
14P4_SS_RXAI/OMultiplexed I/O & Peripheral Pin P4_SS_RXA (General)
15NCI/OMultiplexed I/O & Peripheral Pin NC (General)
16P4_HS_DPI/OMultiplexed I/O & Peripheral Pin P4_HS_DP (General)
17P4_HS_DMI/OMultiplexed I/O & Peripheral Pin P4_HS_DM (General)
18OVCUR2#I/OMultiplexed I/O & Peripheral Pin OVCUR2# (General)
19PWREN2I/OMultiplexed I/O & Peripheral Pin PWREN2 (General)
20VDD5PowerPower Supply Input (VDD5 — 3.3V / 5.0V Standard Logic)
21VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
22NCI/OMultiplexed I/O & Peripheral Pin NC (General)
23PWREN_POLI/OMultiplexed I/O & Peripheral Pin PWREN_POL (General)
24RESET#ISystem Enable & Hardware Reset (RESET#)
25OVCUR1#I/OMultiplexed I/O & Peripheral Pin OVCUR1# (General)
26PWREN1I/OMultiplexed I/O & Peripheral Pin PWREN1 (General)
27OVCUR4#I/OMultiplexed I/O & Peripheral Pin OVCUR4# (General)
28PWREN4I/OMultiplexed I/O & Peripheral Pin PWREN4 (General)
29AVDD33PowerPower Supply Input (AVDD33 — 3.3V / 5.0V Standard Logic)
30GPIO3I/OMultiplexed I/O & Peripheral Pin GPIO3 (General)
31GPIO2I/OMultiplexed I/O & Peripheral Pin GPIO2 (General)
32LED_A4/SPI_SCSI/OMultiplexed I/O & Peripheral Pin LED_A4/SPI_SCS (SPI)
33LED_A3/SPI_MISO/BC_EN#I/OMultiplexed I/O & Peripheral Pin LED_A3/SPI_MISO/BC_EN# (SPI)
34LED_A2/SPI_SCKI/OMultiplexed I/O & Peripheral Pin LED_A2/SPI_SCK (SPI)
35LED_A1/SPI_MOSII/OMultiplexed I/O & Peripheral Pin LED_A1/SPI_MOSI (SPI)
36SMBCLK/GPIO1I/OMultiplexed I/O & Peripheral Pin SMBCLK/GPIO1 (General)
37NCI/OMultiplexed I/O & Peripheral Pin NC (General)
38VDD5PowerPower Supply Input (VDD5 — 3.3V / 5.0V Standard Logic)
39VSWI/OMultiplexed I/O & Peripheral Pin VSW (General)
40VFBI/OMultiplexed I/O & Peripheral Pin VFB (General)
41OVCUR3#I/OMultiplexed I/O & Peripheral Pin OVCUR3# (General)
42PWREN3I/OMultiplexed I/O & Peripheral Pin PWREN3 (General)
43VIO33I/OMultiplexed I/O & Peripheral Pin VIO33 (General)
44PWRON_DETI/OMultiplexed I/O & Peripheral Pin PWRON_DET (General)
45VBUS_DETPowerPower Supply Input (VBUS_DET — 3.3V / 5.0V Standard Logic)
46DVDD12PowerPower Supply Input (DVDD12 — 3.3V / 5.0V Standard Logic)
47UP_SS_TXBI/OMultiplexed I/O & Peripheral Pin UP_SS_TXB (General)
48UP_SS_TXAI/OMultiplexed I/O & Peripheral Pin UP_SS_TXA (General)
49UP_VDD12PowerPower Supply Input (UP_VDD12 — 3.3V / 5.0V Standard Logic)
50UP_SS_RXBI/OMultiplexed I/O & Peripheral Pin UP_SS_RXB (General)
51UP_SS_RXAI/OMultiplexed I/O & Peripheral Pin UP_SS_RXA (General)
52NCI/OMultiplexed I/O & Peripheral Pin NC (General)
53UP_HS_DPI/OMultiplexed I/O & Peripheral Pin UP_HS_DP (General)
54UP_HS_DMI/OMultiplexed I/O & Peripheral Pin UP_HS_DM (General)
55XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
56NCI/OMultiplexed I/O & Peripheral Pin NC (General)
57GNDGNDExposed Thermal & Ground Pad (GND)
58NCI/OMultiplexed I/O & Peripheral Pin NC (General)
59P3_SS_TXBI/OMultiplexed I/O & Peripheral Pin P3_SS_TXB (General)
60P3_SS_TXAI/OMultiplexed I/O & Peripheral Pin P3_SS_TXA (General)
61P3_VDD12PowerPower Supply Input (P3_VDD12 — 3.3V / 5.0V Standard Logic)
62P3_SS_RXBI/OMultiplexed I/O & Peripheral Pin P3_SS_RXB (General)
63P3_SS_RXAI/OMultiplexed I/O & Peripheral Pin P3_SS_RXA (General)
64NCI/OMultiplexed I/O & Peripheral Pin NC (General)
65P3_HS_DPI/OMultiplexed I/O & Peripheral Pin P3_HS_DP (General)
66P3_HS_DMI/OMultiplexed I/O & Peripheral Pin P3_HS_DM (General)
67NCI/OMultiplexed I/O & Peripheral Pin NC (General)
68P2_SS_TXBI/OMultiplexed I/O & Peripheral Pin P2_SS_TXB (General)
69P2_SS_TXAI/OMultiplexed I/O & Peripheral Pin P2_SS_TXA (General)
70P2_VDD12PowerPower Supply Input (P2_VDD12 — 3.3V / 5.0V Standard Logic)
71P2_SS_RXBI/OMultiplexed I/O & Peripheral Pin P2_SS_RXB (General)
72P2_SS_RXAI/OMultiplexed I/O & Peripheral Pin P2_SS_RXA (General)
73NCI/OMultiplexed I/O & Peripheral Pin NC (General)
74P2_HS_DPI/OMultiplexed I/O & Peripheral Pin P2_HS_DP (General)
75P2_HS_DMI/OMultiplexed I/O & Peripheral Pin P2_HS_DM (General)
76NCI/OMultiplexed I/O & Peripheral Pin NC (General)
77GNDGNDGround Reference Pin (GND)
PIN 1 NC
I/O
Multiplexed I/O & Peripheral Pin NC (General)
Design note: Notconnect suggestedsuspension ,
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH634W7V (WCH · QFN-76(9x9))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH634W7V (QFN-76(9x9)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH634W7V (QFN-76(9x9)) - 2. Standard Pinout (Top View)
True package pinout (77 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH634W7V (QFN-76(9x9)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH634W7V (QFN-76(9x9)) - 4. Package Dimensions (D×E×A)
QFN-76(9x9) · 9.00×9.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH634W7V (QFN-76(9x9)) - 5. Recommended Land Pattern
IPC-7351B Footprint (77 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH634W7V (QFN-76(9x9)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH634
P1 · p01_fig011772×1873px
CH634W7V (QFN-76(9x9)) — 1. Pinouts
1. Pinouts
P1 · p01_fig01P1
CH634W7V (QFN-76(9x9)) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P2 · p02_fig011763×1979px
CH634W7V (QFN-76(9x9)) — CH634 Datasheet 2 https://wch-ic.com
CH634 Datasheet 2 https://wch-ic.com
P2 · p02_fig01P2
CH634W7V (QFN-76(9x9)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P5 · p05_fig011856×692px
CH634W7V (QFN-76(9x9)) — Pin No.(See pin with the same
Pin No.(See pin with the same
P27 · p27_fig01All Packages in PDF
CH634W7V (QFN-76(9x9)) — 3.1 QFN56
3.1 QFN56

Technical Specifications & Part Details (CH634W7V)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH634W7V (QFN-76(9x9)) is a 76-pin standard electronic & interconnect component featuring a 9.00 × 9.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, I2C, RTC/CLK, SPI interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
9.00 × 9.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-76(9x9))
Pin Count & Lead PitchN / e
76 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, I2C, RTC/CLK, SPI
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol77 auto-grouped pins
OK
IPC-7351B Land Pattern77 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 6.40×6.40mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-76(9x9))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
9.00 × 9.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.80 mm
Pins / Total PadsTopology
77P / 77Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-76(9x9)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH634W7V (QFN-76(9x9))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH634W7V (QFN-76(9x9))?

Manufactured by WCH, the CH634W7V is housed in a QFN-76(9x9) package with 77 pins and a 0.40 mm lead pitch. Key pins include: 1 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 2 (P1_SS_TXA: Multiplexed I/O & Peripheral Pin P1_SS_TXA (General)), 3 (P1_VDD12: Power Supply Input (P1_VDD12 — 3.3V / 5.0V Standard Logic)), 4 (P1_SS_RXB: Multiplexed I/O & Peripheral Pin P1_SS_RXB (General)), 5 (P1_SS_RXA: Multiplexed I/O & Peripheral Pin P1_SS_RXA (General)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).

What are the IPC-7351B PCB Footprint dimensions for CH634W7V?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH634W7V (QFN-76(9x9)) has a nominal body envelope of 9.00 × 9.00 mm, pitch e = 0.40 mm, and 77 copper pads plus a central exposed thermal pad (EPAD) of 6.40 × 6.40 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH634W7V?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH634W7V (WCH, QFN-76(9x9)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (77 pins) & CH634 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
2P1_SS_TXADigital_IOSignal terminal P1_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_SS_TXA. Supported peripheral buses: General.
3P1_VDD12Power_InPrimary positive power supply input (P1_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4P1_SS_RXBDigital_IOSignal terminal P1_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_SS_RXB. Supported peripheral buses: General.
5P1_SS_RXADigital_IOSignal terminal P1_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_SS_RXA. Supported peripheral buses: General.
6NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
7P1_HS_DPDigital_IOSignal terminal P1_HS_DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_HS_DP. Supported peripheral buses: General.
8P1_HS_DMDigital_IOSignal terminal P1_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_HS_DM. Supported peripheral buses: General.
9NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
10P4_SS_TXBDigital_IOSignal terminal P4_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_TXB. Supported peripheral buses: General.
11P4_SS_TXADigital_IOSignal terminal P4_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_TXA. Supported peripheral buses: General.
12P4_VDD12Power_InPrimary positive power supply input (P4_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
13P4_SS_RXBDigital_IOSignal terminal P4_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_RXB. Supported peripheral buses: General.
14P4_SS_RXADigital_IOSignal terminal P4_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_RXA. Supported peripheral buses: General.
15NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
16P4_HS_DPDigital_IOSignal terminal P4_HS_DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_HS_DP. Supported peripheral buses: General.
17P4_HS_DMDigital_IOSignal terminal P4_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_HS_DM. Supported peripheral buses: General.
18OVCUR2#Digital_IOSignal terminal OVCUR2# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR2#. Supported peripheral buses: General.
19PWREN2Digital_IOSignal terminal PWREN2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN2. Supported peripheral buses: General.
20VDD5Power_InPrimary positive power supply input (VDD5) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
21VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
22NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
23PWREN_POLDigital_IOSignal terminal PWREN_POL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN_POL. Supported peripheral buses: General.
24RESET#Digital_IOActive-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals.
25OVCUR1#Digital_IOSignal terminal OVCUR1# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR1#. Supported peripheral buses: General.
26PWREN1Digital_IOSignal terminal PWREN1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN1. Supported peripheral buses: General.
27OVCUR4#Digital_IOSignal terminal OVCUR4# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR4#. Supported peripheral buses: General.
28PWREN4Digital_IOSignal terminal PWREN4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN4. Supported peripheral buses: General.
29AVDD33Power_InPrimary positive power supply input (AVDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
30GPIO3Digital_IOSignal terminal GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO3. Supported peripheral buses: General.
31GPIO2Digital_IOSignal terminal GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO2. Supported peripheral buses: General.
32LED_A4/SPI_SCSDigital_IOSignal terminal LED_A4/SPI_SCS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_A4/SPI_SCS. Supported peripheral buses: SPI.
33LED_A3/SPI_MISO/BC_EN#Digital_IOSignal terminal LED_A3/SPI_MISO/BC_EN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_A3/SPI_MISO/BC_EN#. Supported peripheral buses: SPI.
34LED_A2/SPI_SCKDigital_IOSignal terminal LED_A2/SPI_SCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_A2/SPI_SCK. Supported peripheral buses: SPI.
35LED_A1/SPI_MOSIDigital_IOSignal terminal LED_A1/SPI_MOSI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_A1/SPI_MOSI. Supported peripheral buses: SPI.
36SMBCLK/GPIO1Digital_IOSignal terminal SMBCLK/GPIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SMBCLK/GPIO1. Supported peripheral buses: General.
37NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
38VDD5Power_InPrimary positive power supply input (VDD5) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
39VSWDigital_IOSignal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: General.
40VFBDigital_IOSignal terminal VFB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VFB. Supported peripheral buses: General.
41OVCUR3#Digital_IOSignal terminal OVCUR3# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR3#. Supported peripheral buses: General.
42PWREN3Digital_IOSignal terminal PWREN3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN3. Supported peripheral buses: General.
43VIO33Digital_IOSignal terminal VIO33 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO33. Supported peripheral buses: General.
44PWRON_DETDigital_IOSignal terminal PWRON_DET (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWRON_DET. Supported peripheral buses: General.
45VBUS_DETPower_InPrimary positive power supply input (VBUS_DET) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
46DVDD12Power_InPrimary positive power supply input (DVDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
47UP_SS_TXBDigital_IOSignal terminal UP_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP_SS_TXB. Supported peripheral buses: General.
48UP_SS_TXADigital_IOSignal terminal UP_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP_SS_TXA. Supported peripheral buses: General.
49UP_VDD12Power_InPrimary positive power supply input (UP_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
50UP_SS_RXBDigital_IOSignal terminal UP_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP_SS_RXB. Supported peripheral buses: General.
51UP_SS_RXADigital_IOSignal terminal UP_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP_SS_RXA. Supported peripheral buses: General.
52NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
53UP_HS_DPDigital_IOSignal terminal UP_HS_DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP_HS_DP. Supported peripheral buses: General.
54UP_HS_DMDigital_IOSignal terminal UP_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP_HS_DM. Supported peripheral buses: General.
55XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
56NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
57GNDGNDBottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
58NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
59P3_SS_TXBDigital_IOSignal terminal P3_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_TXB. Supported peripheral buses: General.
60P3_SS_TXADigital_IOSignal terminal P3_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_TXA. Supported peripheral buses: General.
61P3_VDD12Power_InPrimary positive power supply input (P3_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
62P3_SS_RXBDigital_IOSignal terminal P3_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_RXB. Supported peripheral buses: General.
63P3_SS_RXADigital_IOSignal terminal P3_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_RXA. Supported peripheral buses: General.
64NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
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