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CH132C (QFN-20-EP(2x2)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH132C

WCHID: C46061831QFN-20-EP(2x2) · 21 Pins · Pitch 0.32mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH132C (QFN-20-EP(2x2))1VDDIO2GND3VDD334NXT5STP6DIR7CLK8XO9XI10D011D121GND20D+19D -18RESET#17D716D615D514D413D312D2Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.220.315.210.25.10-5.1-10.2-15.2-20.3mm
2. 2D FOOTPRINT
123456789101112131415161718192021E=2.00mm · Pitch e=0.32mmD=2.00mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 2.00mm × 2.00mm · Pitch: 0.32mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (21/21)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
2GNDGNDGround Reference Pin (GND)
3VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
4NXTI/OMultiplexed I/O & Peripheral Pin NXT (General)
5STPI/OMultiplexed I/O & Peripheral Pin STP (General)
6DIRI/OMultiplexed I/O & Peripheral Pin DIR (General)
7CLKI/OMultiplexed I/O & Peripheral Pin CLK (General)
8XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
9XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
10D0I/OMultiplexed I/O & Peripheral Pin D0 (General)
11D1I/OMultiplexed I/O & Peripheral Pin D1 (General)
12D2I/OMultiplexed I/O & Peripheral Pin D2 (General)
13D3I/OMultiplexed I/O & Peripheral Pin D3 (General)
14D4I/OMultiplexed I/O & Peripheral Pin D4 (General)
15D5I/OMultiplexed I/O & Peripheral Pin D5 (General)
16D6I/OMultiplexed I/O & Peripheral Pin D6 (General)
17D7I/OMultiplexed I/O & Peripheral Pin D7 (General)
18RESET#ISystem Enable & Hardware Reset (RESET#)
19D -I/OMultiplexed I/O & Peripheral Pin D - (General)
20D+I/OMultiplexed I/O & Peripheral Pin D+ (USB)
21GNDGNDGround Reference Pin (GND)
PIN 1 VDDIO
Power
Power Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH132C (WCH · QFN-20-EP(2x2))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH132C (QFN-20-EP(2x2)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH132C (QFN-20-EP(2x2)) - 2. Standard Pinout (Top View)
True package pinout (21 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH132C (QFN-20-EP(2x2)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH132C (QFN-20-EP(2x2)) - 4. Package Dimensions (D×E×A)
QFN-20-EP(2x2) · 2.00×2.00mm · Pitch 0.32mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH132C (QFN-20-EP(2x2)) - 5. Recommended Land Pattern
IPC-7351B Footprint (21 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH132C (QFN-20-EP(2x2)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH132
P1 · p01_fig01309×165px
CH132C (QFN-20-EP(2x2)) — 概述
概述
P1 · p01_fig021750×1156px
CH132C (QFN-20-EP(2x2)) — - 12 Pin 的ULPI 接口，1.8V～3.3V IO 电平，60MHz 时钟
- 12 Pin 的ULPI 接口，1.8V～3.3V IO 电平，60MHz 时钟
P2 · p02_fig011538×2240px
CH132C (QFN-20-EP(2x2)) — 图1-1 引脚分布
图1-1 引脚分布
P18 · p18_fig011402×1534px
CH132C (QFN-20-EP(2x2)) — CH132 作为MCU 或FPGA 的USB PHY，需连接12 根信号线。RESET#引脚是可选连接，默认为悬空，
CH132 作为MCU 或FPGA 的USB PHY，需连接12 根信号线。RESET#引脚是可选连接，默认为悬空，
P18 · p18_fig01P18
CH132C (QFN-20-EP(2x2)) — Datasheet Page 18 (p18_fig01)
Datasheet Page 18 (p18_fig01)
P19 · p19_fig011729×1187px
CH132C (QFN-20-EP(2x2)) — 但C2 需要适当加大，例如10uF 并联0.1uF，并且VBUS 需加过压保护器件。
但C2 需要适当加大，例如10uF 并联0.1uF，并且VBUS 需加过压保护器件。

Technical Specifications & Part Details (CH132C)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH132C (QFN-20-EP(2x2)) is a 20-pin standard electronic & interconnect component featuring a 2.00 × 2.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
60MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
2.00 × 2.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-20-EP(2x2))
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol21 auto-grouped pins
OK
IPC-7351B Land Pattern21 pads · Pitch 0.32mm
OK
IPC-7525 60% Solder PasteEPAD 1.20×1.20mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-20-EP(2x2))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
2.00 × 2.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.32mm
Pad Size (W × L)Level B
0.18 × 0.60 mm
Pins / Total PadsTopology
21P / 21Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-20-EP(2x2)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH132C (QFN-20-EP(2x2))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH132C (QFN-20-EP(2x2))?

Manufactured by WCH, the CH132C is housed in a QFN-20-EP(2x2) package with 21 pins and a 0.32 mm lead pitch. Key pins include: 1 (VDDIO: Power Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)), 2 (GND: Ground Reference Pin (GND)), 3 (VDD33: Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)), 4 (NXT: Multiplexed I/O & Peripheral Pin NXT (General)), 5 (STP: Multiplexed I/O & Peripheral Pin STP (General)), 6 (DIR: Multiplexed I/O & Peripheral Pin DIR (General)).

What are the IPC-7351B PCB Footprint dimensions for CH132C?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH132C (QFN-20-EP(2x2)) has a nominal body envelope of 2.00 × 2.00 mm, pitch e = 0.32 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 1.20 × 1.20 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH132C?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH132C (WCH, QFN-20-EP(2x2)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (21 pins) & CH132 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
3VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4NXTDigital_IOSignal terminal NXT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NXT. Supported peripheral buses: General.
5STPDigital_IOSignal terminal STP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: STP. Supported peripheral buses: General.
6DIRDigital_IOSignal terminal DIR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIR. Supported peripheral buses: General.
7CLKDigital_IOSignal terminal CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLK. Supported peripheral buses: General.
8XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
9XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
10D0Digital_IOSignal terminal D0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D0. Supported peripheral buses: General.
11D1Digital_IOSignal terminal D1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D1. Supported peripheral buses: General.
12D2Digital_IOSignal terminal D2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D2. Supported peripheral buses: General.
13D3Digital_IOSignal terminal D3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D3. Supported peripheral buses: General.
14D4Digital_IOSignal terminal D4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D4. Supported peripheral buses: General.
15D5Digital_IOSignal terminal D5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D5. Supported peripheral buses: General.
16D6Digital_IOSignal terminal D6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D6. Supported peripheral buses: General.
17D7Digital_IOSignal terminal D7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D7. Supported peripheral buses: General.
18RESET#Digital_IOActive-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals.
19D -Digital_IOSignal terminal D - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D -. Supported peripheral buses: General.
20D+Digital_IOSignal terminal D+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D+. Supported peripheral buses: USB.
21GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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