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STM32C092ECY6TR (WLCSP24) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32C092ECY6TR

STID: C45338512WLCSP24 · 24 Pins · Pitch 0.31mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32C092ECY6TR (WLCSP24)A1PA15A3PB3/PB5A5PB4/PB6A7PC14-OSCX_INB2PA14-BOOT0B4PB7/PB8B6PC15-OSCX_OUC1PB1C3PA13C5PA0C7VDD/VDDAD2PA4G7PA2G5PA5G3PA7G1PB2/PA8F6PA3F4PA6F2PA11[PA9]E7PF2-NRSTE5PA1E3PB0E1PA12[PA10]D6VSS/VSSAGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.820.315.210.25.10-5.1-10.2-15.2-20.3mm
2. 2D FOOTPRINT
A1A3A5A7B2B4B6C1C3C5C7D2D6E1E3E5E7F2F4F6G1G3G5G7E=1.70mm · Pitch e=0.31mmD=2.60mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 1.70mm × 2.60mm · Pitch: 0.31mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (24/24)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
A3PB3/PB5I/OMultiplexed I/O & Peripheral Pin PB3/PB5 (General)
A5PB4/PB6I/OMultiplexed I/O & Peripheral Pin PB4/PB6 (General)
A7PC14-OSCX_INI/OMultiplexed I/O & Peripheral Pin PC14-OSCX_IN (RTC/CLK)
B2PA14-BOOT0I/OMultiplexed I/O & Peripheral Pin PA14-BOOT0 (General)
B4PB7/PB8I/OMultiplexed I/O & Peripheral Pin PB7/PB8 (General)
B6PC15-OSCX_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSCX_OUT (RTC/CLK)
C1PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
C3PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
C5PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
C7VDD/VDDAPowerPower Supply Input (VDD/VDDA — 3.3V VDD (Max 4.0V))
D2PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
D6VSS/VSSAGNDGround Reference Pin (VSS/VSSA)
E1PA12[PA10]I/OMultiplexed I/O & Peripheral Pin PA12[PA10] (General)
E3PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
E5PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
E7PF2-NRSTI/OMultiplexed I/O & Peripheral Pin PF2-NRST (General)
F2PA11[PA9]I/OMultiplexed I/O & Peripheral Pin PA11[PA9] (General)
F4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
F6PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
G1PB2/PA8I/OMultiplexed I/O & Peripheral Pin PB2/PA8 (General)
G3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
G5PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
G7PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
PIN A1 PA15
I/O
Multiplexed I/O & Peripheral Pin PA15 (General)
Design note: Signal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32C092ECY6TR (ST · WLCSP24)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32C092ECY6TR (WLCSP24) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32C092ECY6TR (WLCSP24) - 2. Standard Pinout (Top View)
True package pinout (24 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32C092ECY6TR (WLCSP24) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32C092ECY6TR (WLCSP24) - 4. Package Dimensions (D×E×A)
WLCSP24 · 1.70×2.60mm · Pitch 0.31mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32C092ECY6TR (WLCSP24) - 5. Recommended Land Pattern
IPC-7351B Footprint (24 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32C092ECY6TR (WLCSP24) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (STM32C092ECY6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32C092ECY6TR (WLCSP24) is a 20-pin embedded microcontroller unit (mcu) featuring a 2.60 × 1.70 × 0.55 mm mechanical envelope (lead pitch e = 0.35 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
2.60 × 1.70 × 0.55 mm (A1=0.18 mm)
Package family: WLCSP (WLCSP24)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.35 mm (13.8 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol24 auto-grouped pins
OK
IPC-7351B Land Pattern24 pads · Pitch 0.31mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP24)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
2.60 × 1.70 mm
Height (A) & Pitch (e)IPC-7351B
A=0.55mm · e=0.31mm
Pad Size (W × L)Level B
0.16 × 0.16 mm
Pins / Total PadsTopology
24P / 24Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP24
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32C092ECY6TR (WLCSP24)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32C092ECY6TR (WLCSP24)?

Manufactured by ST, the STM32C092ECY6TR is housed in a WLCSP24 package with 24 pins and a 0.31 mm lead pitch. Key pins include: A1 (PA15: Multiplexed I/O & Peripheral Pin PA15 (General)), A3 (PB3/PB5: Multiplexed I/O & Peripheral Pin PB3/PB5 (General)), A5 (PB4/PB6: Multiplexed I/O & Peripheral Pin PB4/PB6 (General)), A7 (PC14-OSCX_IN: Multiplexed I/O & Peripheral Pin PC14-OSCX_IN (RTC/CLK)), B2 (PA14-BOOT0: Multiplexed I/O & Peripheral Pin PA14-BOOT0 (General)), B4 (PB7/PB8: Multiplexed I/O & Peripheral Pin PB7/PB8 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32C092ECY6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32C092ECY6TR (WLCSP24) has a nominal body envelope of 1.70 × 2.60 mm, pitch e = 0.31 mm, and 24 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32C092ECY6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32C092ECY6TR (ST, WLCSP24) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (24 pins) & STM32C091 / STM32C092 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
A3PB3/PB5Digital_IOSignal terminal PB3/PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3/PB5. Supported peripheral buses: General.
A5PB4/PB6Digital_IOSignal terminal PB4/PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4/PB6. Supported peripheral buses: General.
A7PC14-OSCX_INDigital_IOSignal terminal PC14-OSCX_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSCX_IN. Supported peripheral buses: RTC/CLK.
B2PA14-BOOT0Digital_IOSignal terminal PA14-BOOT0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14-BOOT0. Supported peripheral buses: General.
B4PB7/PB8Digital_IOSignal terminal PB7/PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7/PB8. Supported peripheral buses: General.
B6PC15-OSCX_OUTDigital_IOSignal terminal PC15-OSCX_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15-OSCX_OUT. Supported peripheral buses: RTC/CLK.
C1PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
C3PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
C5PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
C7VDD/VDDAPower_InPrimary positive power supply input (VDD/VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D2PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
D6VSS/VSSAGND0V electrical ground return terminal (VSS/VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
E1PA12[PA10]Digital_IOSignal terminal PA12[PA10] (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12[PA10]. Supported peripheral buses: General.
E3PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
E5PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
E7PF2-NRSTDigital_IOSignal terminal PF2-NRST (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2-NRST. Supported peripheral buses: General.
F2PA11[PA9]Digital_IOSignal terminal PA11[PA9] (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11[PA9]. Supported peripheral buses: General.
F4PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
F6PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
G1PB2/PA8Digital_IOSignal terminal PB2/PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2/PA8. Supported peripheral buses: General.
G3PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
G5PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
G7PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
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