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CH585F (QFN-32(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH585F

WCHID: C42381475QFN-32(4x4) · 33 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH585F (QFN-32(4x4))1PA102VDCID3VSW4VDD335PB9/NFCI/PA96PB9（4） PB87PB178PB169PB15（3）I/O/510PB14（3）I/O/511PB1312PB1213PB1114PB1015PB716PB617PB533EP32PA1131PA1230PA13/SCK0/PW29PA14/MOSI/TX28PA15/MISO/RX27PA5/TXD3/A126PA4/RXD3/A025VDCIA24ANT23VINTA22X32MI21X32MO20PB2219IO2018PB4Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.227.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233E=4.00mm · Pitch e=0.40mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
2VDCIDI/OMultiplexed I/O & Peripheral Pin VDCID (General)
3VSWI/OMultiplexed I/O & Peripheral Pin VSW (General)
4VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
5PB9/NFCI/PA9/TMR0/A13I/OMultiplexed I/O & Peripheral Pin PB9/NFCI/PA9/TMR0/A13 (General)
6PB9（4） PB8I/OMultiplexed I/O & Peripheral Pin PB9（4） PB8 (General)
7PB17I/OMultiplexed I/O & Peripheral Pin PB17 (General)
8PB16I/OMultiplexed I/O & Peripheral Pin PB16 (General)
9PB15（3）I/O/5VTPowerPower Supply Input (PB15（3）I/O/5VT — 3.3V / 5.0V Standard Logic)
10PB14（3）I/O/5VTPowerPower Supply Input (PB14（3）I/O/5VT — 3.3V / 5.0V Standard Logic)
11PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, I2C)
12PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, I2C)
13PB11I/OMultiplexed I/O & Peripheral Pin PB11 (USB)
14PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
15PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, PWM)
16PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, PWM)
17PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART)
18PB4I/OMultiplexed I/O & Peripheral Pin PB4 (UART, PWM)
19IO20I/OGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20PB22I/OMultiplexed I/O & Peripheral Pin PB22 (UART)
21X32MOI/OMultiplexed I/O & Peripheral Pin X32MO (General)
22X32MII/OMultiplexed I/O & Peripheral Pin X32MI (General)
23VINTAPowerPower Supply Input (VINTA — 3.3V / 5.0V Standard Logic)
24ANTI/OMultiplexed I/O & Peripheral Pin ANT (General)
25VDCIAI/OMultiplexed I/O & Peripheral Pin VDCIA (General)
26PA4/RXD3/A0I/OMultiplexed I/O & Peripheral Pin PA4/RXD3/A0 (UART)
27PA5/TXD3/A1I/OMultiplexed I/O & Peripheral Pin PA5/TXD3/A1 (UART)
28PA15/MISO/RXD0_/A5I/OMultiplexed I/O & Peripheral Pin PA15/MISO/RXD0_/A5 (UART, SPI)
29PA14/MOSI/TXD0_/A4I/OMultiplexed I/O & Peripheral Pin PA14/MOSI/TXD0_/A4 (UART, SPI)
30PA13/SCK0/PWM5/A3I/OMultiplexed I/O & Peripheral Pin PA13/SCK0/PWM5/A3 (SPI, PWM)
31PA12I/OMultiplexed I/O & Peripheral Pin PA12 (PWM)
32PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
33EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 PA10
I/O
Multiplexed I/O & Peripheral Pin PA10 (General)
Design note: X32KI /TMR1
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH585F (WCH · QFN-32(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH585F (QFN-32(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH585F (QFN-32(4x4)) - 2. Standard Pinout (Top View)
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH585F (QFN-32(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH585F (QFN-32(4x4)) - 4. Package Dimensions (D×E×A)
QFN-32(4x4) · 4.00×4.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH585F (QFN-32(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH585F (QFN-32(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)
Showing 1–11 of 11 uncropped original figures for CH584 / CH585
P1 · p01_fig01247×133px
CH585F (QFN-32(4x4)) — 概述
概述
P3 · p03_fig011128×1216px
CH585F (QFN-32(4x4)) — 2 3
2 3
P3 · p03_fig021132×1128px
CH585F (QFN-32(4x4)) — V1.6 1
V1.6 1
P5 · p05_fig011107×1221px
CH585F (QFN-32(4x4)) — 3 2 3 3
3 2 3 3
P5 · p05_fig021077×1222px
CH585F (QFN-32(4x4)) — 1
1
P5 · p05_fig02P5
CH585F (QFN-32(4x4)) — Datasheet Page 5 (p05_fig02)
Datasheet Page 5 (p05_fig02)
P103 · p103_fig011708×557px
CH585F (QFN-32(4x4)) — CH585/CH584 数据手册 https://wch.cn
CH585/CH584 数据手册 https://wch.cn
P103 · p103_fig021609×396px
CH585F (QFN-32(4x4)) — 12.11 I2C 时序
12.11 I2C 时序
P103 · p103_fig031731×740px
CH585F (QFN-32(4x4)) — | TSsTA | SOARARAZATSCL Maat | 04 | | | us | THSTA | SDATKRBAZIa SCL mRBEAOORESRT] | 04 | | us | TSDA | SCL.EAAZAT SDA MIABAUMESEAA | 0.05 | | |S | THA | SCL_EAIAZ Ia SDABRBOIRERTIA] | >toni@ | | |S | TssTO | SOAFAAZ AN SCL MraeAMAtA | 04 |
| TSsTA | SOARARAZATSCL Maat | 04 | | | us | THSTA | SDATKRBAZIa SCL mRBEAOORESRT] | 04 | | us | TSDA | SCL.EAAZAT SDA MIABAUMESEAA | 0.05 | | |S | THA | SCL_EAIAZ Ia SDABRBOIRERTIA] | >toni@ | | |S | TssTO | SOAFAAZ AN SCL MraeAMAtA | 04 |
P103 · p103_fig01P103
CH585F (QFN-32(4x4)) — Datasheet Page 103 (p103_fig01)
Datasheet Page 103 (p103_fig01)
P109 · p109_fig011713×1927px
CH585F (QFN-32(4x4)) — V1.6 107
V1.6 107

Technical Specifications & Part Details (CH585F)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH585F (QFN-32(4x4)) is a 32-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, UART, SPI, I2C, ADC, PWM interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
4GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-32(4x4))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, UART, SPI, I2C, ADC, PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol33 auto-grouped pins
OK
IPC-7351B Land Pattern33 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 2.70×2.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-32(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-32(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH585F (QFN-32(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH585F (QFN-32(4x4))?

Manufactured by WCH, the CH585F is housed in a QFN-32(4x4) package with 33 pins and a 0.40 mm lead pitch. Key pins include: 1 (PA10: Multiplexed I/O & Peripheral Pin PA10 (General)), 2 (VDCID: Multiplexed I/O & Peripheral Pin VDCID (General)), 3 (VSW: Multiplexed I/O & Peripheral Pin VSW (General)), 4 (VDD33: Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)), 5 (PB9/NFCI/PA9/TMR0/A13: Multiplexed I/O & Peripheral Pin PB9/NFCI/PA9/TMR0/A13 (General)), 6 (PB9（4） PB8: Multiplexed I/O & Peripheral Pin PB9（4） PB8 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH585F?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH585F (QFN-32(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.40 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 2.70 × 2.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH585F?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH585F (WCH, QFN-32(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & CH584 / CH585 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
2VDCIDDigital_IOSignal terminal VDCID (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VDCID. Supported peripheral buses: General.
3VSWDigital_IOSignal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: General.
4VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
5PB9/NFCI/PA9/TMR0/A13Digital_IOSignal terminal PB9/NFCI/PA9/TMR0/A13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9/NFCI/PA9/TMR0/A13. Supported peripheral buses: General.
6PB9（4） PB8Digital_IOSignal terminal PB9（4） PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9（4） PB8. Supported peripheral buses: General.
7PB17Digital_IOSignal terminal PB17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB17. Supported peripheral buses: General.
8PB16Digital_IOSignal terminal PB16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB16. Supported peripheral buses: General.
9PB15（3）I/O/5VTPower_InPrimary positive power supply input (PB15（3）I/O/5VT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
10PB14（3）I/O/5VTPower_InPrimary positive power supply input (PB14（3）I/O/5VT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
11PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: UART, SPI, I2C.
12PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: UART, I2C.
13PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: USB.
14PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
15PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: UART, PWM.
16PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART, PWM.
17PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: UART.
18PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: UART, PWM.
19IO20Digital_IOGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20PB22Digital_IOSignal terminal PB22 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB22. Supported peripheral buses: UART.
21X32MODigital_IOSignal terminal X32MO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MO. Supported peripheral buses: General.
22X32MIDigital_IOSignal terminal X32MI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MI. Supported peripheral buses: General.
23VINTAPower_InPrimary positive power supply input (VINTA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
24ANTRF_50OhmSignal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General.
25VDCIADigital_IOSignal terminal VDCIA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VDCIA. Supported peripheral buses: General.
26PA4/RXD3/A0Digital_IOSignal terminal PA4/RXD3/A0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4/RXD3/A0. Supported peripheral buses: UART.
27PA5/TXD3/A1Digital_IOSignal terminal PA5/TXD3/A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5/TXD3/A1. Supported peripheral buses: UART.
28PA15/MISO/RXD0_/A5Digital_IOSignal terminal PA15/MISO/RXD0_/A5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: UART, SPI.
29PA14/MOSI/TXD0_/A4Digital_IOSignal terminal PA14/MOSI/TXD0_/A4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: UART, SPI.
30PA13/SCK0/PWM5/A3Digital_IOSignal terminal PA13/SCK0/PWM5/A3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI, PWM.
31PA12Digital_IOSignal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12. Supported peripheral buses: PWM.
32PA11Digital_IOSignal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
33EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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