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STM32WBA50KGU6 (UFQFPN-32(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32WBA50KGU6

STUFQFPN-32(5x5) · 33 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32WBA50KGU6 (UFQFPN-32(5x5))1PB122PA83PA74PA65VDDA6PA57PA28PA19PA010PB911PB812PC15OSC32 OU13PC14OSC32 IN14VDD15PB416PB317PA1533VSS(exposedp32VCAP31VDD30VDDRFPA29OSC_IN28OSC_OUT27VDDRF26VDDHPA25RF24NRST23VDD22PH3BOOT0 -21PB1520PA1219PA1318PA14Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.827.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233E=5.00mm · Pitch e=0.50mmD=5.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
2PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, SPI, ADC, RTC/CLK)
3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (I2C, ADC)
4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, I2C, ADC)
5VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
6PA5I/OMultiplexed I/O & Peripheral Pin PA5 (UART, SPI, ADC)
7PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC)
8PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC)
9PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM)
10PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI, ADC)
11PB8I/OMultiplexed I/O & Peripheral Pin PB8 (PWM)
12PC15OSC32 OUT -_I/OMultiplexed I/O & Peripheral Pin PC15OSC32 OUT -_ (RTC/CLK)
13PC14OSC32 IN -_I/OMultiplexed I/O & Peripheral Pin PC14OSC32 IN -_ (RTC/CLK)
14VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
15PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SWD/JTAG)
16PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SWD/JTAG)
17PA15I/OMultiplexed I/O & Peripheral Pin PA15 (SWD/JTAG)
18PA14I/OMultiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
19PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
20PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
21PB15I/OMultiplexed I/O & Peripheral Pin PB15 (I2C)
22PH3BOOT0 -I/OMultiplexed I/O & Peripheral Pin PH3BOOT0 - (General)
23VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
24NRSTISystem Enable & Hardware Reset (NRST)
25RFI/OMultiplexed I/O & Peripheral Pin RF (General)
26VDDHPAPowerPower Supply Input (VDDHPA — 3.3V VDD (Max 4.0V))
27VDDRFPowerPower Supply Input (VDDRF — 3.3V VDD (Max 4.0V))
28OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
29OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
30VDDRFPAPowerPower Supply Input (VDDRFPA — 3.3V VDD (Max 4.0V))
31VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
32VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
33VSS(exposedpad)GNDGround Reference Pin (VSS(exposedpad))
PIN 1 PB12
I/O
Multiplexed I/O & Peripheral Pin PB12 (General)
Design note: Alt: TIM2 CH1 TIM2_ETRUSART1TX ,_ ,_ , TSC_SYNCEVENTOUT ,
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32WBA50KGU6 (ST · UFQFPN-32(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32WBA50KGU6 (UFQFPN-32(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32WBA50KGU6 (UFQFPN-32(5x5)) - 2. Standard Pinout (Top View)
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32WBA50KGU6 (UFQFPN-32(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32WBA50KGU6 (UFQFPN-32(5x5)) - 4. Package Dimensions (D×E×A)
UFQFPN-32(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32WBA50KGU6 (UFQFPN-32(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32WBA50KGU6 (UFQFPN-32(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for STM32WBA50
P1 · p01_fig01EXACT PACKAGE
STM32WBA50KGU6 (UFQFPN-32(5x5)) — • Core: Arm® 32-bit Cortex®-M33 CPU with MPU, DSP, and FPU
• Core: Arm® 32-bit Cortex®-M33 CPU with MPU, DSP, and FPU
P51 · p51_fig01EXACT PACKAGE
STM32WBA50KGU6 (UFQFPN-32(5x5)) — Figure 6. UFQFPN32 pinout(1) (2)
Figure 6. UFQFPN32 pinout(1) (2)
P105 · p105_fig01EXACT PACKAGE
STM32WBA50KGU6 (UFQFPN-32(5x5)) — Figure 27. UFQFPN32 - Outline D
Figure 27. UFQFPN32 - Outline D
P106 · p106_fig01EXACT PACKAGE
STM32WBA50KGU6 (UFQFPN-32(5x5)) — Figure 28. UFQFPN32 - Recommended footprint
Figure 28. UFQFPN32 - Recommended footprint
P58 · p58_fig011546×1398px
STM32WBA50KGU6 (UFQFPN-32(5x5)) — Figure 9. Power supply scheme
Figure 9. Power supply scheme
P79 · p79_fig011546×698px
STM32WBA50KGU6 (UFQFPN-32(5x5)) — Figure 12. LSE typical application with a crystal
Figure 12. LSE typical application with a crystal
P79 · p79_fig021559×504px
STM32WBA50KGU6 (UFQFPN-32(5x5)) — Figure 13. LSE external square clock source AC timing diagram VLSE_ext tLSE = 1/fLSE
Figure 13. LSE external square clock source AC timing diagram VLSE_ext tLSE = 1/fLSE
P96 · p96_fig011547×755px
STM32WBA50KGU6 (UFQFPN-32(5x5)) — Figure 19. Typical connection diagram when using the ADC
Figure 19. Typical connection diagram when using the ADC

Technical Specifications & Part Details (STM32WBA50KGU6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32WBA50KGU6 (UFQFPN-32(5x5)) is a 32-pin embedded microcontroller unit (mcu) featuring a 5.00 × 5.00 × 0.55 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, SPI, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
18 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.55 mm (A1=0.04 mm)
Package family: QFN (UFQFPN-32(5x5))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, SPI, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol33 auto-grouped pins
OK
IPC-7351B Land Pattern33 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 3.45×3.45mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFQFPN-32(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.55mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 0.75 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFQFPN-32(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32WBA50KGU6 (UFQFPN-32(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32WBA50KGU6 (UFQFPN-32(5x5))?

Manufactured by ST, the STM32WBA50KGU6 is housed in a UFQFPN-32(5x5) package with 33 pins and a 0.50 mm lead pitch. Key pins include: 1 (PB12: Multiplexed I/O & Peripheral Pin PB12 (General)), 2 (PA8: Multiplexed I/O & Peripheral Pin PA8 (UART, SPI, ADC, RTC/CLK)), 3 (PA7: Multiplexed I/O & Peripheral Pin PA7 (I2C, ADC)), 4 (PA6: Multiplexed I/O & Peripheral Pin PA6 (UART, SPI, I2C, ADC)), 5 (VDDA: Power Supply Input (VDDA — 3.3V VDD (Max 4.0V))), 6 (PA5: Multiplexed I/O & Peripheral Pin PA5 (UART, SPI, ADC)).

What are the IPC-7351B PCB Footprint dimensions for STM32WBA50KGU6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32WBA50KGU6 (UFQFPN-32(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 3.45 × 3.45 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32WBA50KGU6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32WBA50KGU6 (ST, UFQFPN-32(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & STM32WBA50 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
2PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_RDY. Supported peripheral buses: UART, SPI, ADC, RTC/CLK.
3PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: I2C, ADC.
4PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL, SPI3_RDY. Supported peripheral buses: UART, SPI, I2C, ADC.
5VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
6PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_NSS. Supported peripheral buses: UART, SPI, ADC.
7PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC.
8PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC.
9PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, PWM.
10PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO_LPUART1RTSDE. Supported peripheral buses: SPI, ADC.
11PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: PWM.
12PC15OSC32 OUT -_Digital_IOSignal terminal PC15OSC32 OUT -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15OSC32 OUT -_. Supported peripheral buses: RTC/CLK.
13PC14OSC32 IN -_Digital_IOSignal terminal PC14OSC32 IN -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14OSC32 IN -_. Supported peripheral buses: RTC/CLK.
14VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
15PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: SWD/JTAG.
16PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: SWD/JTAG.
17PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: SWD/JTAG.
18PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: SWD/JTAG.
19PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
20PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
21PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: I2C.
22PH3BOOT0 -Digital_IOSignal terminal PH3BOOT0 - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH3BOOT0 -. Supported peripheral buses: General.
23VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
24NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
25RFRF_50OhmSignal terminal RF (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: RF. Supported peripheral buses: General.
26VDDHPAPower_InPrimary positive power supply input (VDDHPA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
27VDDRFPower_InPrimary positive power supply input (VDDRF) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
28OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
29OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
30VDDRFPAPower_InPrimary positive power supply input (VDDRFPA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
31VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
32VCAPDigital_IOSignal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
33VSS(exposedpad)GND0V electrical ground return terminal (VSS(exposedpad)) for internal core logic, I/O drivers, and analog sub-blocks.
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