![CH571R (TSSOP-16) — 位 名称 访问 描述 复位值 [7：0] R8_SPI0_FIFO_COUNT RW 当前FIFO 中字节计数。 00h SPI 收发FIFO 计数寄存器(R8_SPI0_FIFO_COUNT1) | 位 名称 访问 描述 复位值 | [7：0] R8_SPI0_FIFO_COUNT1 RW 当前FIFO 中字节计数。 同R8_SPI0_FIFO_COUNT。 00h | SPI 收发数据总长度寄存器(R16_SPI0_TOTAL_CNT) | 位 名称 访问 描述 复位值](/api/v1/assets/C39831291/extracted/figures/p63_fig01.png)
Mechanical Dimensions & Land Pattern (TSSOP-16)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit TSSOP-16 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH571R (TSSOP-16)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH571R (TSSOP-16)?
Manufactured by WCH, the CH571R is housed in a TSSOP-16 package with 16 pins and a 0.65 mm lead pitch. Key pins include: 1 (PA15/MISO/RXD0_/AIN5: Multiplexed I/O & Peripheral Pin PA15/MISO/RXD0_/AIN5 (UART, SPI, ADC)), 2 (PA14/MOSI/TXD0_/AIN4: Multiplexed I/O & Peripheral Pin PA14/MOSI/TXD0_/AIN4 (UART, SPI, ADC)), 3 (PA13/SCK0/AIN3: Multiplexed I/O & Peripheral Pin PA13/SCK0/AIN3 (SPI, ADC)), 4 (PA12/SCS/AIN2: Multiplexed I/O & Peripheral Pin PA12/SCS/AIN2 (ADC)), 5 (VIO33/VDD33: Power Supply Input (VIO33/VDD33 — 3.3V / 5.0V Standard Logic)), 6 (PA8/RXD1: Multiplexed I/O & Peripheral Pin PA8/RXD1 (UART)).
What are the IPC-7351B PCB Footprint dimensions for CH571R?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH571R (TSSOP-16) has a nominal body envelope of 4.40 × 5.00 mm, pitch e = 0.65 mm, and 16 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH571R?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH571R (WCH, TSSOP-16) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (16 pins) & CH571 / CH573 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PA15/MISO/RXD0_/AIN5 | Digital_IO | Signal terminal PA15/MISO/RXD0_/AIN5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15/MISO/RXD0_/AIN5. Supported peripheral buses: UART, SPI, ADC. |
| 2 | PA14/MOSI/TXD0_/AIN4 | Digital_IO | Signal terminal PA14/MOSI/TXD0_/AIN4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14/MOSI/TXD0_/AIN4. Supported peripheral buses: UART, SPI, ADC. |
| 3 | PA13/SCK0/AIN3 | Digital_IO | Signal terminal PA13/SCK0/AIN3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13/SCK0/AIN3. Supported peripheral buses: SPI, ADC. |
| 4 | PA12/SCS/AIN2 | Analog | Signal terminal PA12/SCS/AIN2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12/SCS/AIN2. Supported peripheral buses: ADC. |
| 5 | VIO33/VDD33 | Power_In | Primary positive power supply input (VIO33/VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 6 | PA8/RXD1 | Digital_IO | Signal terminal PA8/RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8/RXD1. Supported peripheral buses: UART. |
| 7 | PA9/TMR0/TXD1 | Digital_IO | Signal terminal PA9/TMR0/TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9/TMR0/TXD1. Supported peripheral buses: UART. |
| 8 | PB11/UD+/TMR2_ | Digital_IO | Signal terminal PB11/UD+/TMR2_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11/UD+/TMR2_. Supported peripheral buses: USB. |
| 9 | PB10/UD-/TMR1_ | Digital_IO | Signal terminal PB10/UD-/TMR1_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10/UD-/TMR1_. Supported peripheral buses: USB. |
| 10 | PB23/RST#/TMR0_ | Digital_IO | Signal terminal PB23/RST#/TMR0_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB23/RST#/TMR0_. Supported peripheral buses: General. |
| 11 | PB22/TMR3 | Digital_IO | Signal terminal PB22/TMR3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB22/TMR3. Supported peripheral buses: General. |
| 12 | X32MO | Digital_IO | Signal terminal X32MO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MO. Supported peripheral buses: General. |
| 13 | X32MI | Digital_IO | Signal terminal X32MI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MI. Supported peripheral buses: General. |
| 14 | VINTA | Power_In | Primary positive power supply input (VINTA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 15 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 16 | ANT | RF_50Ohm | Signal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General. |