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CH9142 (QFN-28(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9142

WCHID: C39831289QFN-28(4x4) · 29 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9142 (QFN-28(4x4))0GND1X32KO2X32KI3VDD_D4VSW5VCC6AT07NC8RTS1#/TNOW19CTS110TXD111RXD112RTS0/TNOW013CTS0#14TXD028BLEDTA127BLESTA026AT125LED124SLEEP23LED0/RELOAD22VDD_A21ANT20VINTA19X32MI18X32MO17NC16RST#15RXD0Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.225.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
028272625242322212019181716151413121110981237654E=4.00mm · Pitch e=0.40mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
0GNDGNDGround Reference Pin (GND)
1X32KOI/OMultiplexed I/O & Peripheral Pin X32KO (General)
2X32KII/OMultiplexed I/O & Peripheral Pin X32KI (General)
3VDD_DPowerPower Supply Input (VDD_D — 3.3V / 5.0V Standard Logic)
4VSWI/OMultiplexed I/O & Peripheral Pin VSW (General)
5VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
6AT0I/OMultiplexed I/O & Peripheral Pin AT0 (General)
7NCI/OMultiplexed I/O & Peripheral Pin NC (General)
8RTS1#/TNOW1I/OMultiplexed I/O & Peripheral Pin RTS1#/TNOW1 (UART)
9CTS1I/OMultiplexed I/O & Peripheral Pin CTS1 (UART)
10TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
11RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
12RTS0/TNOW0I/OMultiplexed I/O & Peripheral Pin RTS0/TNOW0 (UART)
13CTS0#I/OMultiplexed I/O & Peripheral Pin CTS0# (UART)
14TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
15RXD0I/OMultiplexed I/O & Peripheral Pin RXD0 (UART)
16RST#I/OMultiplexed I/O & Peripheral Pin RST# (General)
17NCI/OMultiplexed I/O & Peripheral Pin NC (General)
18X32MOI/OMultiplexed I/O & Peripheral Pin X32MO (General)
19X32MII/OMultiplexed I/O & Peripheral Pin X32MI (General)
20VINTAPowerPower Supply Input (VINTA — 3.3V / 5.0V Standard Logic)
21ANTI/OMultiplexed I/O & Peripheral Pin ANT (General)
22VDD_APowerPower Supply Input (VDD_A — 3.3V / 5.0V Standard Logic)
23LED0/RELOADI/OMultiplexed I/O & Peripheral Pin LED0/RELOAD (General)
24SLEEPI/OMultiplexed I/O & Peripheral Pin SLEEP (General)
25LED1I/OMultiplexed I/O & Peripheral Pin LED1 (General)
26AT1I/OMultiplexed I/O & Peripheral Pin AT1 (General)
27BLESTA0I/OMultiplexed I/O & Peripheral Pin BLESTA0 (General)
28BLEDTA1I/OMultiplexed I/O & Peripheral Pin BLEDTA1 (General)
PIN 0 GND
GND
Ground Reference Pin (GND)
Design note: 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9142 (WCH · QFN-28(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9142 (QFN-28(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9142 (QFN-28(4x4)) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9142 (QFN-28(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9142 (QFN-28(4x4)) - 4. Package Dimensions (D×E×A)
QFN-28(4x4) · 4.00×4.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9142 (QFN-28(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9142 (QFN-28(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for CH9142
P2 · p02_fig02EXACT PACKAGE
CH9142 (QFN-28(4x4)) — 封装形式 塑体尺寸 引脚间距 封装说明 订货型号 | QFN28 4*4mm 0.4mm 15.7mil 方形无引线 28 脚 CH9142 | 4、引脚 | QFN28 引脚号 引脚名称 类型 引脚说明 | 0 GND P 电源地 | 1 X32K0 A 低频振荡器的反相输出端 | 2 X32KI A 低频振荡器的反相输入端 | 3 VDD_D P 电源，需外接2.2uF 退耦电容 | 4 VSW P 内部DC-DC 开关输出 | 5 VCC P 芯片电源输入，需外接2.2
封装形式 塑体尺寸 引脚间距 封装说明 订货型号 | QFN28 4*4mm 0.4mm 15.7mil 方形无引线 28 脚 CH9142 | 4、引脚 | QFN28 引脚号 引脚名称 类型 引脚说明 | 0 GND P 电源地 | 1 X32K0 A 低频振荡器的反相输出端 | 2 X32KI A 低频振荡器的反相输入端 | 3 VDD_D P 电源，需外接2.2uF 退耦电容 | 4 VSW P 内部DC-DC 开关输出 | 5 VCC P 芯片电源输入，需外接2.2
P1 · p01_fig011567×653px
CH9142 (QFN-28(4x4)) — 图1 两个蓝牙主机通过CH9142 两个蓝牙从机与串口设备进行通讯框图 图2 CH9142 蓝牙主从模式连接外部从机和主机进行通讯框图 2、特点  支持蓝牙主机模式、蓝牙从机模式和蓝牙广播模式。  支持串口AT 配置和蓝牙传输配置。
图1 两个蓝牙主机通过CH9142 两个蓝牙从机与串口设备进行通讯框图 图2 CH9142 蓝牙主从模式连接外部从机和主机进行通讯框图 2、特点  支持蓝牙主机模式、蓝牙从机模式和蓝牙广播模式。  支持串口AT 配置和蓝牙传输配置。
P1 · p01_fig021726×714px
CH9142 (QFN-28(4x4)) — 图2 CH9142 蓝牙主从模式连接外部从机和主机进行通讯框图 2、特点  支持蓝牙主机模式、蓝牙从机模式和蓝牙广播模式。  支持串口AT 配置和蓝牙传输配置。
图2 CH9142 蓝牙主从模式连接外部从机和主机进行通讯框图 2、特点  支持蓝牙主机模式、蓝牙从机模式和蓝牙广播模式。  支持串口AT 配置和蓝牙传输配置。
P2 · p02_fig01639×638px
CH9142 (QFN-28(4x4)) — 封装形式 塑体尺寸 引脚间距 封装说明 订货型号
封装形式 塑体尺寸 引脚间距 封装说明 订货型号
P2 · p02_fig01P2
CH9142 (QFN-28(4x4)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P2 · p02_fig02P2
CH9142 (QFN-28(4x4)) — Datasheet Page 2 (p02_fig02)
Datasheet Page 2 (p02_fig02)
P3 · p03_fig011752×1986px
CH9142 (QFN-28(4x4)) — 两个串口共享蓝牙接口进行通讯，可实现蓝牙双从机模式、单从机模式、一主一从模式、双主机 模式和广播模式，串口对应的角色可以通过配置进行设定。
两个串口共享蓝牙接口进行通讯，可实现蓝牙双从机模式、单从机模式、一主一从模式、双主机 模式和广播模式，串口对应的角色可以通过配置进行设定。

Technical Specifications & Part Details (CH9142)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9142 (QFN-28(4x4)) is a 28-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-28(4x4))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 2.70×2.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-28(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.70 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-28(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9142 (QFN-28(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9142 (QFN-28(4x4))?

Manufactured by WCH, the CH9142 is housed in a QFN-28(4x4) package with 29 pins and a 0.40 mm lead pitch. Key pins include: 0 (GND: Ground Reference Pin (GND)), 1 (X32KO: Multiplexed I/O & Peripheral Pin X32KO (General)), 2 (X32KI: Multiplexed I/O & Peripheral Pin X32KI (General)), 3 (VDD_D: Power Supply Input (VDD_D — 3.3V / 5.0V Standard Logic)), 4 (VSW: Multiplexed I/O & Peripheral Pin VSW (General)), 5 (VCC: Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)).

What are the IPC-7351B PCB Footprint dimensions for CH9142?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9142 (QFN-28(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.40 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 2.70 × 2.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9142?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9142 (WCH, QFN-28(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & CH9142 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
0GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
1X32KODigital_IOSignal terminal X32KO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32KO. Supported peripheral buses: General.
2X32KIDigital_IOSignal terminal X32KI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32KI. Supported peripheral buses: General.
3VDD_DPower_InPrimary positive power supply input (VDD_D) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4VSWDigital_IOSignal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: General.
5VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
6AT0Digital_IOSignal terminal AT0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AT0. Supported peripheral buses: General.
7NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
8RTS1#/TNOW1Digital_IOSignal terminal RTS1#/TNOW1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS1#/TNOW1. Supported peripheral buses: UART.
9CTS1Digital_IOSignal terminal CTS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS1. Supported peripheral buses: UART.
10TXD1Digital_IOSignal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
11RXD1Digital_IOSignal terminal RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART.
12RTS0/TNOW0Digital_IOSignal terminal RTS0/TNOW0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS0/TNOW0. Supported peripheral buses: UART.
13CTS0#Digital_IOSignal terminal CTS0# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS0#. Supported peripheral buses: UART.
14TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
15RXD0Digital_IOSignal terminal RXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD0. Supported peripheral buses: UART.
16RST#Digital_IOSignal terminal RST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST#. Supported peripheral buses: General.
17NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
18X32MODigital_IOSignal terminal X32MO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MO. Supported peripheral buses: General.
19X32MIDigital_IOSignal terminal X32MI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MI. Supported peripheral buses: General.
20VINTAPower_InPrimary positive power supply input (VINTA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
21ANTRF_50OhmSignal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General.
22VDD_APower_InPrimary positive power supply input (VDD_A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
23LED0/RELOADDigital_IOSignal terminal LED0/RELOAD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED0/RELOAD. Supported peripheral buses: General.
24SLEEPDigital_IOSignal terminal SLEEP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SLEEP. Supported peripheral buses: General.
25LED1Digital_IOSignal terminal LED1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED1. Supported peripheral buses: General.
26AT1Digital_IOSignal terminal AT1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AT1. Supported peripheral buses: General.
27BLESTA0Digital_IOSignal terminal BLESTA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BLESTA0. Supported peripheral buses: General.
28BLEDTA1Digital_IOSignal terminal BLEDTA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BLEDTA1. Supported peripheral buses: General.
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