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CH9434A (QFN-48(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9434A

WCHID: C39831286QFN-48(5x5) · 49 Pins · Pitch 0.35mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9434A (QFN-48(5x5))1PIN12 PIN13 2PIN5 PIN6 、3PIN9 PIN10 、4PIN7 PIN8 、5PIN2 PIN3 、6PIN14 PIN15 7-8PIN149PIN1610DCD1#/GPIO2311CTS1#/GPIO212/TNOW113IO1514/TNOW015/TNOW116/TNOW317TXD018DTR1/GPIO819DSR1/GPIO920RXD021RI1#/GPIO1022DCD2#/GPIO1123DTR2#/GPIO1224DSR2#/GPIO1325RST49GND48RTS0#/TNOW0/47CTS0#/GPIO046SCS#45SCK44SDI43SDO42GPIO2441DCD0#/GPIO1940RI3#/GPIO1839INT#38RXD237TXD336RXD335VDD34NC33VCORE32XI31XO30DSR3#/GPIO1729DTR3#/GPIO1628DCD3#/GPIO1527RI2#/GPIO1426NCGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
49484746454443424140393837363534333231302928272625242322212019181716151413121110987654321E=5.00mm · Pitch e=0.35mmD=5.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.35mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PIN12 PIN13 、I/OMultiplexed I/O & Peripheral Pin PIN12 PIN13 、 (UART)
2PIN5 PIN6 、I/OMultiplexed I/O & Peripheral Pin PIN5 PIN6 、 (UART)
3PIN9 PIN10 、I/OMultiplexed I/O & Peripheral Pin PIN9 PIN10 、 (UART)
4PIN7 PIN8 、I/OMultiplexed I/O & Peripheral Pin PIN7 PIN8 、 (UART)
5PIN2 PIN3 、I/OMultiplexed I/O & Peripheral Pin PIN2 PIN3 、 (RTC/CLK)
6PIN14 PIN15 、I/OMultiplexed I/O & Peripheral Pin PIN14 PIN15 、 (CAN)
7-I/OMultiplexed I/O & Peripheral Pin - (General)
8PIN14I/OMultiplexed I/O & Peripheral Pin PIN14 (UART)
9PIN16I/OMultiplexed I/O & Peripheral Pin PIN16 (UART)
10DCD1#/GPIO23I/OMultiplexed I/O & Peripheral Pin DCD1#/GPIO23 (General)
11CTS1#/GPIO2I/OMultiplexed I/O & Peripheral Pin CTS1#/GPIO2 (UART)
12/TNOW1I/OMultiplexed I/O & Peripheral Pin /TNOW1 (UART)
13IO15I/OGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14/TNOW0I/OMultiplexed I/O & Peripheral Pin /TNOW0 (UART)
15/TNOW1I/OMultiplexed I/O & Peripheral Pin /TNOW1 (UART)
16/TNOW3I/OMultiplexed I/O & Peripheral Pin /TNOW3 (UART)
17TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
18DTR1/GPIO8I/OMultiplexed I/O & Peripheral Pin DTR1/GPIO8 (UART)
19DSR1/GPIO9I/OMultiplexed I/O & Peripheral Pin DSR1/GPIO9 (UART)
20RXD0I/OMultiplexed I/O & Peripheral Pin RXD0 (UART)
21RI1#/GPIO10I/OMultiplexed I/O & Peripheral Pin RI1#/GPIO10 (General)
22DCD2#/GPIO11I/OMultiplexed I/O & Peripheral Pin DCD2#/GPIO11 (General)
23DTR2#/GPIO12I/OMultiplexed I/O & Peripheral Pin DTR2#/GPIO12 (UART)
24DSR2#/GPIO13I/OMultiplexed I/O & Peripheral Pin DSR2#/GPIO13 (UART)
25RSTI/OMultiplexed I/O & Peripheral Pin RST (General)
26NCI/OMultiplexed I/O & Peripheral Pin NC (General)
27RI2#/GPIO14I/OMultiplexed I/O & Peripheral Pin RI2#/GPIO14 (General)
28DCD3#/GPIO15I/OMultiplexed I/O & Peripheral Pin DCD3#/GPIO15 (General)
29DTR3#/GPIO16I/OMultiplexed I/O & Peripheral Pin DTR3#/GPIO16 (UART)
30DSR3#/GPIO17I/OMultiplexed I/O & Peripheral Pin DSR3#/GPIO17 (UART)
31XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
32XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
33VCOREI/OMultiplexed I/O & Peripheral Pin VCORE (General)
34NCI/OMultiplexed I/O & Peripheral Pin NC (General)
35VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
36RXD3I/OMultiplexed I/O & Peripheral Pin RXD3 (UART)
37TXD3I/OMultiplexed I/O & Peripheral Pin TXD3 (UART)
38RXD2I/OMultiplexed I/O & Peripheral Pin RXD2 (UART)
39INT#I/OMultiplexed I/O & Peripheral Pin INT# (General)
40RI3#/GPIO18I/OMultiplexed I/O & Peripheral Pin RI3#/GPIO18 (General)
41DCD0#/GPIO19I/OMultiplexed I/O & Peripheral Pin DCD0#/GPIO19 (General)
42GPIO24I/OMultiplexed I/O & Peripheral Pin GPIO24 (General)
43SDOI/OMultiplexed I/O & Peripheral Pin SDO (General)
44SDII/OMultiplexed I/O & Peripheral Pin SDI (General)
45SCKI/OMultiplexed I/O & Peripheral Pin SCK (SPI)
46SCS#I/OMultiplexed I/O & Peripheral Pin SCS# (General)
47CTS0#/GPIO0I/OMultiplexed I/O & Peripheral Pin CTS0#/GPIO0 (UART)
48RTS0#/TNOW0/GPIO1I/OMultiplexed I/O & Peripheral Pin RTS0#/TNOW0/GPIO1 (UART)
49GNDGNDExposed Thermal & Ground Pad (GND)
PIN 1 PIN12 PIN13 、
I/O
Multiplexed I/O & Peripheral Pin PIN12 PIN13 、 (UART)
Design note: UART0_TXRX_
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 17 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9434A (WCH · QFN-48(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9434A (QFN-48(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9434A (QFN-48(5x5)) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9434A (QFN-48(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9434A (QFN-48(5x5)) - 4. Package Dimensions (D×E×A)
QFN-48(5x5) · 5.00×5.00mm · Pitch 0.35mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9434A (QFN-48(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9434A (QFN-48(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (17 figures · Page 1/2)
Showing 1–12 of 17 uncropped original figures for CH9434
P1 · p01_fig011493×518px
CH9434A (QFN-48(5x5)) — CH9434D 是一款SPI/IIC 转四串口和一路CAN 扩展芯片，提供四组全双工的9 线异步串口，用于 单片机/嵌入式系统扩展异步串口。CH9434D 包含四个兼容16C550 的异步串口，最高支持6Mbps 波特 率通讯。最多支持4 路GPIO，提供半双工收发自动切换引脚TNOW，提供一路CAN 收发控制器。
CH9434D 是一款SPI/IIC 转四串口和一路CAN 扩展芯片，提供四组全双工的9 线异步串口，用于 单片机/嵌入式系统扩展异步串口。CH9434D 包含四个兼容16C550 的异步串口，最高支持6Mbps 波特 率通讯。最多支持4 路GPIO，提供半双工收发自动切换引脚TNOW，提供一路CAN 收发控制器。
P1 · p01_fig021494×619px
CH9434A (QFN-48(5x5)) — 2、特点
2、特点
P1 · p01_fig02P1
CH9434A (QFN-48(5x5)) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P3 · p03_fig011318×1269px
CH9434A (QFN-48(5x5)) — SCS/AD0 11 TXD1 12 RXD1 13 CTS 1/TNOW 1/GPIO 0/CAN_RX 14 RTS 1/TNOW 2/GPIO 1/CAN_TX 15
SCS/AD0 11 TXD1 12 RXD1 13 CTS 1/TNOW 1/GPIO 0/CAN_RX 14 RTS 1/TNOW 2/GPIO 1/CAN_TX 15
P3 · p03_fig021046×1003px
CH9434A (QFN-48(5x5)) — V1.5 3
V1.5 3
P3 · p03_fig01P3
CH9434A (QFN-48(5x5)) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P40 · p40_fig01880×492px
CH9434A (QFN-48(5x5)) — 11.2 初始化串口 例1：CH9434A 初始化串口1 为115200 波特率，8Bit 数据位，1Bit 停止位，无校验。 1)、读出串口1 的LCR 寄存器值，假设读出0x00。
11.2 初始化串口 例1：CH9434A 初始化串口1 为115200 波特率，8Bit 数据位，1Bit 停止位，无校验。 1)、读出串口1 的LCR 寄存器值，假设读出0x00。
P40 · p40_fig02883×492px
CH9434A (QFN-48(5x5)) — 2)、写串口1 的LCR 寄存器值，设DLAB 位，设8Bit 数据位，1Bit 停止位，无校验。
2)、写串口1 的LCR 寄存器值，设DLAB 位，设8Bit 数据位，1Bit 停止位，无校验。
P40 · p40_fig03883×491px
CH9434A (QFN-48(5x5)) — 3)、设置串口1 的波特率除数锁存器DLL 和DLM：32000000*15/13/8/115200≈40，DLL 为0x28， DLM 为0x00。
3)、设置串口1 的波特率除数锁存器DLL 和DLM：32000000*15/13/8/115200≈40，DLL 为0x28， DLM 为0x00。
P40 · p40_fig04883×492px
CH9434A (QFN-48(5x5)) — V1.5 40
V1.5 40
P41 · p41_fig011238×782px
CH9434A (QFN-48(5x5)) — SCS#
SCS#
P41 · p41_fig021238×805px
CH9434A (QFN-48(5x5)) — 例2：CH9434D 初始化串口1 为115200 波特率，8Bit 数据位，1Bit 停止位，无校验。 1)、开启串口1 的引脚功能
例2：CH9434D 初始化串口1 为115200 波特率，8Bit 数据位，1Bit 停止位，无校验。 1)、开启串口1 的引脚功能
Page 1 / 2 (17 extracted figures)

Technical Specifications & Part Details (CH9434A)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9434A (QFN-48(5x5)) is a 48-pin standard electronic & interconnect component featuring a 5.00 × 5.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Wi-Fi, SPI, I2C, CAN, RTC/CLK, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-48(5x5))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, SPI, I2C, CAN, RTC/CLK, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.35mm
OK
IPC-7525 60% Solder PasteEPAD 3.70×3.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — CH9434 (2)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (QFN-48(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.35mm
Pad Size (W × L)Level B
0.16 × 0.80 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-48(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9434A (QFN-48(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9434A (QFN-48(5x5))?

Manufactured by WCH, the CH9434A is housed in a QFN-48(5x5) package with 49 pins and a 0.35 mm lead pitch. Key pins include: 1 (PIN12 PIN13 、: Multiplexed I/O & Peripheral Pin PIN12 PIN13 、 (UART)), 2 (PIN5 PIN6 、: Multiplexed I/O & Peripheral Pin PIN5 PIN6 、 (UART)), 3 (PIN9 PIN10 、: Multiplexed I/O & Peripheral Pin PIN9 PIN10 、 (UART)), 4 (PIN7 PIN8 、: Multiplexed I/O & Peripheral Pin PIN7 PIN8 、 (UART)), 5 (PIN2 PIN3 、: Multiplexed I/O & Peripheral Pin PIN2 PIN3 、 (RTC/CLK)), 6 (PIN14 PIN15 、: Multiplexed I/O & Peripheral Pin PIN14 PIN15 、 (CAN)).

What are the IPC-7351B PCB Footprint dimensions for CH9434A?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9434A (QFN-48(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.35 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 3.70 × 3.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9434A?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9434A (WCH, QFN-48(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & CH9434 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PIN12 PIN13 、Digital_IOSignal terminal PIN12 PIN13 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN12 PIN13 、. Supported peripheral buses: UART.
2PIN5 PIN6 、Digital_IOSignal terminal PIN5 PIN6 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN5 PIN6 、. Supported peripheral buses: UART.
3PIN9 PIN10 、Digital_IOSignal terminal PIN9 PIN10 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN9 PIN10 、. Supported peripheral buses: UART.
4PIN7 PIN8 、Digital_IOSignal terminal PIN7 PIN8 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN7 PIN8 、. Supported peripheral buses: UART.
5PIN2 PIN3 、Digital_IOSignal terminal PIN2 PIN3 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN2 PIN3 、. Supported peripheral buses: RTC/CLK.
6PIN14 PIN15 、Digital_IOSignal terminal PIN14 PIN15 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN14 PIN15 、. Supported peripheral buses: CAN.
7-Digital_IOSignal terminal - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: -. Supported peripheral buses: General.
8PIN14Digital_IOSignal terminal PIN14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN14. Supported peripheral buses: UART.
9PIN16Digital_IOSignal terminal PIN16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIN16. Supported peripheral buses: UART.
10DCD1#/GPIO23Digital_IOSignal terminal DCD1#/GPIO23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD1#/GPIO23. Supported peripheral buses: General.
11CTS1#/GPIO2Digital_IOSignal terminal CTS1#/GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS1#/GPIO2. Supported peripheral buses: UART.
12/TNOW1Digital_IOSignal terminal /TNOW1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: /TNOW1. Supported peripheral buses: UART.
13IO15Digital_IOGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14/TNOW0Digital_IOSignal terminal /TNOW0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: /TNOW0. Supported peripheral buses: UART.
15/TNOW1Digital_IOSignal terminal /TNOW1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: /TNOW1. Supported peripheral buses: UART.
16/TNOW3Digital_IOSignal terminal /TNOW3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: /TNOW3. Supported peripheral buses: UART.
17TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
18DTR1/GPIO8Digital_IOSignal terminal DTR1/GPIO8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR1/GPIO8. Supported peripheral buses: UART.
19DSR1/GPIO9Digital_IOSignal terminal DSR1/GPIO9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR1/GPIO9. Supported peripheral buses: UART.
20RXD0Digital_IOSignal terminal RXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD0. Supported peripheral buses: UART.
21RI1#/GPIO10Digital_IOSignal terminal RI1#/GPIO10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI1#/GPIO10. Supported peripheral buses: General.
22DCD2#/GPIO11Digital_IOSignal terminal DCD2#/GPIO11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD2#/GPIO11. Supported peripheral buses: General.
23DTR2#/GPIO12Digital_IOSignal terminal DTR2#/GPIO12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR2#/GPIO12. Supported peripheral buses: UART.
24DSR2#/GPIO13Digital_IOSignal terminal DSR2#/GPIO13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR2#/GPIO13. Supported peripheral buses: UART.
25RSTDigital_IOSignal terminal RST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST. Supported peripheral buses: General.
26NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
27RI2#/GPIO14Digital_IOSignal terminal RI2#/GPIO14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI2#/GPIO14. Supported peripheral buses: General.
28DCD3#/GPIO15Digital_IOSignal terminal DCD3#/GPIO15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD3#/GPIO15. Supported peripheral buses: General.
29DTR3#/GPIO16Digital_IOSignal terminal DTR3#/GPIO16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR3#/GPIO16. Supported peripheral buses: UART.
30DSR3#/GPIO17Digital_IOSignal terminal DSR3#/GPIO17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR3#/GPIO17. Supported peripheral buses: UART.
31XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
32XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
33VCOREDigital_IOSignal terminal VCORE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCORE. Supported peripheral buses: General.
34NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
35VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
36RXD3Digital_IOSignal terminal RXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD3. Supported peripheral buses: UART.
37TXD3Digital_IOSignal terminal TXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD3. Supported peripheral buses: UART.
38RXD2Digital_IOSignal terminal RXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD2. Supported peripheral buses: UART.
39INT#Digital_IOSignal terminal INT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT#. Supported peripheral buses: General.
40RI3#/GPIO18Digital_IOSignal terminal RI3#/GPIO18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI3#/GPIO18. Supported peripheral buses: General.
41DCD0#/GPIO19Digital_IOSignal terminal DCD0#/GPIO19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD0#/GPIO19. Supported peripheral buses: General.
42GPIO24Digital_IOSignal terminal GPIO24 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO24. Supported peripheral buses: General.
43SDODigital_IOSignal terminal SDO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDO. Supported peripheral buses: General.
44SDIDigital_IOSignal terminal SDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDI. Supported peripheral buses: General.
45SCKDigital_IOSignal terminal SCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCK. Supported peripheral buses: SPI.
46SCS#Digital_IOSignal terminal SCS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCS#. Supported peripheral buses: General.
47CTS0#/GPIO0Digital_IOSignal terminal CTS0#/GPIO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS0#/GPIO0. Supported peripheral buses: UART.
48RTS0#/TNOW0/GPIO1Digital_IOSignal terminal RTS0#/TNOW0/GPIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS0#/TNOW0/GPIO1. Supported peripheral buses: UART.
49GNDGNDBottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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