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LE9643AQCT (QFN-36(4x6)) — Symbol, Footprint IPC-7351B & 3D STEP Model

LE9643AQCT

MICROCHIPID: C3679042QFN-36(4x6) · 37 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · LE9643AQCT (QFN-36(4x6))1VDDSW2DVDD3SWOUTY4FS/ZSYNC5DXA/ZMISO6DRA/ZMOSI7PCLK/ZCLK8DVDD1V29VDDHPI10ZSI#11INT#12DCLK13DIN14DOUT15CS#16VS/IO17IREF18RSVD19RSVD37EP36SWISY35SWCMPY34SWVSY33LFC32RDC31TDC30RAC29TAC28IHL27VREF26RTV25AVDD24RSN123VBAT122TIPD121RINGD120RSVDGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.830.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5mm
2. 2D FOOTPRINT
12345678910111213141516171825262728293031323334353619202122232437E=4.00mm · Pitch e=0.40mmD=6.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 4.00mm × 6.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (37/37)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDDSWPowerPower Supply Input (VDDSW — 3.3V / 5.0V Standard Logic)
2DVDDPowerPower Supply Input (DVDD — 3.3V / 5.0V Standard Logic)
3SWOUTYI/OMultiplexed I/O & Peripheral Pin SWOUTY (General)
4FS/ZSYNCI/OMultiplexed I/O & Peripheral Pin FS/ZSYNC (General)
5DXA/ZMISOI/OMultiplexed I/O & Peripheral Pin DXA/ZMISO (General)
6DRA/ZMOSII/OMultiplexed I/O & Peripheral Pin DRA/ZMOSI (General)
7PCLK/ZCLKI/OMultiplexed I/O & Peripheral Pin PCLK/ZCLK (General)
8DVDD1V2PowerPower Supply Input (DVDD1V2 — 3.3V / 5.0V Standard Logic)
9VDDHPIPowerPower Supply Input (VDDHPI — 3.3V / 5.0V Standard Logic)
10ZSI#I/OMultiplexed I/O & Peripheral Pin ZSI# (General)
11INT#I/OMultiplexed I/O & Peripheral Pin INT# (General)
12DCLKI/OMultiplexed I/O & Peripheral Pin DCLK (General)
13DINI/OMultiplexed I/O & Peripheral Pin DIN (General)
14DOUTI/OMultiplexed I/O & Peripheral Pin DOUT (General)
15CS#I/OMultiplexed I/O & Peripheral Pin CS# (General)
16VS/IOI/OMultiplexed I/O & Peripheral Pin VS/IO (General)
17IREFI/OMultiplexed I/O & Peripheral Pin IREF (General)
18RSVDI/OMultiplexed I/O & Peripheral Pin RSVD (General)
19RSVDI/OMultiplexed I/O & Peripheral Pin RSVD (General)
20RSVDI/OMultiplexed I/O & Peripheral Pin RSVD (General)
21RINGD1I/OMultiplexed I/O & Peripheral Pin RINGD1 (General)
22TIPD1I/OMultiplexed I/O & Peripheral Pin TIPD1 (General)
23VBAT1PowerPower Supply Input (VBAT1 — 3.3V / 5.0V Standard Logic)
24RSN1I/OMultiplexed I/O & Peripheral Pin RSN1 (General)
25AVDDPowerPower Supply Input (AVDD — 3.3V / 5.0V Standard Logic)
26RTVI/OMultiplexed I/O & Peripheral Pin RTV (General)
27VREFAnalogMultiplexed I/O & Peripheral Pin VREF (General)
28IHLI/OMultiplexed I/O & Peripheral Pin IHL (General)
29TACI/OMultiplexed I/O & Peripheral Pin TAC (General)
30RACI/OMultiplexed I/O & Peripheral Pin RAC (General)
31TDCI/OMultiplexed I/O & Peripheral Pin TDC (General)
32RDCI/OMultiplexed I/O & Peripheral Pin RDC (General)
33LFCI/OMultiplexed I/O & Peripheral Pin LFC (General)
34SWVSYI/OMultiplexed I/O & Peripheral Pin SWVSY (General)
35SWCMPYI/OMultiplexed I/O & Peripheral Pin SWCMPY (General)
36SWISYI/OMultiplexed I/O & Peripheral Pin SWISY (General)
37EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 VDDSW
Power
Power Supply Input (VDDSW — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VDDSW) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: LE9643AQCT (MICROCHIP · QFN-36(4x6))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
LE9643AQCT (QFN-36(4x6)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
LE9643AQCT (QFN-36(4x6)) - 2. Standard Pinout (Top View)
True package pinout (37 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
LE9643AQCT (QFN-36(4x6)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LE9643AQCT (QFN-36(4x6)) - 4. Package Dimensions (D×E×A)
QFN-36(4x6) · 4.00×6.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
LE9643AQCT (QFN-36(4x6)) - 5. Recommended Land Pattern
IPC-7351B Footprint (37 Pads)Expand ›
6. Application SchematicSCHEMATIC
LE9643AQCT (QFN-36(4x6)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for LE9643
P7 · p07_fig01EXACT PACKAGE
LE9643AQCT (QFN-36(4x6)) — Figure 4 - Le9643/Le9653 Device Pin Out (36-Pin QFN) - Top View
Figure 4 - Le9643/Le9653 Device Pin Out (36-Pin QFN) - Top View
P1 · p01_fig01960×1163px
LE9643AQCT (QFN-36(4x6)) — Figure 1 - Le9643/Le9653 Block Diagram
Figure 1 - Le9643/Le9653 Block Diagram
P2 · p02_fig011888×810px
LE9643AQCT (QFN-36(4x6)) — Figure 1 - Le9643/Le9653 Solution Diagram
Figure 1 - Le9643/Le9653 Solution Diagram
P6 · p06_fig011911×1730px
LE9643AQCT (QFN-36(4x6)) — Figure 3 shows a typical line interface circuit for the Le9643/53. The ZSI control interface is illustrated. Consult Microsemi for the most recent reference design.
Figure 3 shows a typical line interface circuit for the Le9643/53. The ZSI control interface is illustrated. Consult Microsemi for the most recent reference design.
P9 · p09_fig01451×338px
LE9643AQCT (QFN-36(4x6)) — _ Microsemi.
_ Microsemi.

Technical Specifications & Part Details (LE9643AQCT)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:LE9643AQCT (QFN-36(4x6)) is a 36-pin standard electronic & interconnect component featuring a 6.00 × 4.00 × 0.90 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C to +85°C with integrated SPI interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 4.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-36(4x6))
Pin Count & Lead PitchN / e
36 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol37 auto-grouped pins
OK
IPC-7351B Land Pattern37 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 4.80×2.80mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-36(4x6))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.50 mm
Pins / Total PadsTopology
37P / 37Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-36(4x6)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — LE9643AQCT (QFN-36(4x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of LE9643AQCT (QFN-36(4x6))?

Manufactured by MICROCHIP, the LE9643AQCT is housed in a QFN-36(4x6) package with 37 pins and a 0.40 mm lead pitch. Key pins include: 1 (VDDSW: Power Supply Input (VDDSW — 3.3V / 5.0V Standard Logic)), 2 (DVDD: Power Supply Input (DVDD — 3.3V / 5.0V Standard Logic)), 3 (SWOUTY: Multiplexed I/O & Peripheral Pin SWOUTY (General)), 4 (FS/ZSYNC: Multiplexed I/O & Peripheral Pin FS/ZSYNC (General)), 5 (DXA/ZMISO: Multiplexed I/O & Peripheral Pin DXA/ZMISO (General)), 6 (DRA/ZMOSI: Multiplexed I/O & Peripheral Pin DRA/ZMOSI (General)).

What are the IPC-7351B PCB Footprint dimensions for LE9643AQCT?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), LE9643AQCT (QFN-36(4x6)) has a nominal body envelope of 4.00 × 6.00 mm, pitch e = 0.40 mm, and 37 copper pads plus a central exposed thermal pad (EPAD) of 4.80 × 2.80 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for LE9643AQCT?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for LE9643AQCT (MICROCHIP, QFN-36(4x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (37 pins) & LE9643 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDDSWPower_InPrimary positive power supply input (VDDSW) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2DVDDPower_InPrimary positive power supply input (DVDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3SWOUTYDigital_IOSignal terminal SWOUTY (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SWOUTY. Supported peripheral buses: General.
4FS/ZSYNCDigital_IOSignal terminal FS/ZSYNC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: FS/ZSYNC. Supported peripheral buses: General.
5DXA/ZMISODigital_IOSignal terminal DXA/ZMISO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DXA/ZMISO. Supported peripheral buses: General.
6DRA/ZMOSIDigital_IOSignal terminal DRA/ZMOSI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DRA/ZMOSI. Supported peripheral buses: General.
7PCLK/ZCLKDigital_IOSignal terminal PCLK/ZCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PCLK/ZCLK. Supported peripheral buses: General.
8DVDD1V2Power_InPrimary positive power supply input (DVDD1V2) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
9VDDHPIPower_InPrimary positive power supply input (VDDHPI) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
10ZSI#Digital_IOSignal terminal ZSI# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ZSI#. Supported peripheral buses: General.
11INT#Digital_IOSignal terminal INT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT#. Supported peripheral buses: General.
12DCLKDigital_IOSignal terminal DCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCLK. Supported peripheral buses: General.
13DINDigital_IOSignal terminal DIN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIN. Supported peripheral buses: General.
14DOUTDigital_IOSignal terminal DOUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DOUT. Supported peripheral buses: General.
15CS#Digital_IOSignal terminal CS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS#. Supported peripheral buses: General.
16VS/IODigital_IOSignal terminal VS/IO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VS/IO. Supported peripheral buses: General.
17IREFDigital_IOSignal terminal IREF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IREF. Supported peripheral buses: General.
18RSVDNCSignal terminal RSVD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD. Supported peripheral buses: General.
19RSVDNCSignal terminal RSVD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD. Supported peripheral buses: General.
20RSVDNCSignal terminal RSVD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD. Supported peripheral buses: General.
21RINGD1Digital_IOSignal terminal RINGD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RINGD1. Supported peripheral buses: General.
22TIPD1Digital_IOSignal terminal TIPD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TIPD1. Supported peripheral buses: General.
23VBAT1Power_InPrimary positive power supply input (VBAT1) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
24RSN1Digital_IOSignal terminal RSN1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSN1. Supported peripheral buses: General.
25AVDDPower_InPrimary positive power supply input (AVDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
26RTVDigital_IOSignal terminal RTV (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTV. Supported peripheral buses: General.
27VREFAnalogSignal terminal VREF (Analog, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VREF. Supported peripheral buses: General.
28IHLDigital_IOSignal terminal IHL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IHL. Supported peripheral buses: General.
29TACDigital_IOSignal terminal TAC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TAC. Supported peripheral buses: General.
30RACDigital_IOSignal terminal RAC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RAC. Supported peripheral buses: General.
31TDCDigital_IOSignal terminal TDC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TDC. Supported peripheral buses: General.
32RDCDigital_IOSignal terminal RDC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RDC. Supported peripheral buses: General.
33LFCDigital_IOSignal terminal LFC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LFC. Supported peripheral buses: General.
34SWVSYDigital_IOSignal terminal SWVSY (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SWVSY. Supported peripheral buses: General.
35SWCMPYDigital_IOSignal terminal SWCMPY (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SWCMPY. Supported peripheral buses: General.
36SWISYDigital_IOSignal terminal SWISY (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SWISY. Supported peripheral buses: General.
37EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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