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STM32WLE4JCI6 (UFBGA-73) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32WLE4JCI6

STID: C3606718UFBGA-73 · 73 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32WLE4JCI6 (UFBGA-73)A1VSSSMPSA2VDDSMPSA4PA14A5VDDAA7VDDA8VBATA9PA12B1VLXSMPSB2VFBSMPSB3PA15B4PB15B5VREF+B6PC14OSC32 INB7VSSB8PA13B9PA11C1PB3C2PB4C3PB7C4PB9C5PC15 - OSC32C6PB14C7PC13C8PA10D2PB5D3PB8D4PC2D5PC3D6PA0D7PB13D8PB2D9VSSE1PB6E2VDDE3VSSE4PC5E5PA9J9RFO_HPJ8RFO_LPJ6RFI_PJ5PH3BOOT0 -J3PA8J2PA5J1PA4H9VR_PAH8VDDPAH7RFI_NH6VSSRFH5VDDH4PB10H3PA7H2PA2H1PA3G9OSC_ING8VSSRFG7VSSRFG6VSSRFG5VSSG4PB11G3PA1G2PC6F8OSC_OUTF7VDDRF1V55F6PB0 VDD TCXOF5NRSTF4PA6F3PC4F2PC0F1PC1E9VDDE8VDDRFE7PB1E6PB12Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.853.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3mm
2. 2D FOOTPRINT
A1B1C1E1F1H1J1A2B2C2D2E2F2G2H2J2B3C3D3E3F3G3H3J3A4B4C4D4E4F4G4H4A5B5C5D5E5F5G5H5J5B6C6D6E6F6G6H6J6A7B7C7D7E7F7G7H7A8B8C8D8E8F8G8H8J8A9B9D9E9G9H9J9E=5.00mm · Pitch e=0.50mmD=5.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (73/73)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VSSSMPSGNDGround Reference Pin (VSSSMPS)
A2VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
A4PA14I/OMultiplexed I/O & Peripheral Pin PA14 (I2C, ADC, SWD/JTAG)
A5VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
A7VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
A8VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
A9PA12I/OMultiplexed I/O & Peripheral Pin PA12 (I2C, ADC)
B1VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
B2VFBSMPSI/OMultiplexed I/O & Peripheral Pin VFBSMPS (General)
B3PA15I/OMultiplexed I/O & Peripheral Pin PA15 (I2C, ADC, SWD/JTAG)
B4PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, PWM)
B5VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
B6PC14OSC32 IN -_I/OMultiplexed I/O & Peripheral Pin PC14OSC32 IN -_ (RTC/CLK)
B7VSSGNDGround Reference Pin (VSS)
B8PA13I/OMultiplexed I/O & Peripheral Pin PA13 (I2C, ADC, SWD/JTAG)
B9PA11I/OMultiplexed I/O & Peripheral Pin PA11 (SPI, ADC, PWM)
C1PB3I/OMultiplexed I/O & Peripheral Pin PB3 (UART, SPI, ADC, SWD/JTAG)
C2PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI, I2C, SWD/JTAG)
C3PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C)
C4PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI, PWM)
C5PC15 - OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK)
C6PB14I/OMultiplexed I/O & Peripheral Pin PB14 (I2C, ADC, PWM)
C7PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
C8PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, SPI, I2C, DAC, RTC/CLK)
D2PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, SPI)
D3PB8I/OMultiplexed I/O & Peripheral Pin PB8 (PWM)
D4PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
D5PC3I/OMultiplexed I/O & Peripheral Pin PC3 (SPI)
D6PA0I/OMultiplexed I/O & Peripheral Pin PA0 (PWM)
D7PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, ADC, PWM)
D8PB2I/OMultiplexed I/O & Peripheral Pin PB2 (SPI, ADC)
D9VSSGNDGround Reference Pin (VSS)
E1PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART)
E2VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E3VSSGNDGround Reference Pin (VSS)
E4PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
E5PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, SPI, I2C, PWM)
E6PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI)
E7PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART)
E8VDDRFPowerPower Supply Input (VDDRF — 3.3V VDD (Max 4.0V))
E9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F1PC1I/OMultiplexed I/O & Peripheral Pin PC1 (SPI, I2C)
F2PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
F3PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
F4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI)
F5NRSTISystem Enable & Hardware Reset (NRST)
F6PB0 VDD TCXO -_PowerRegulated Power Output (PB0 VDD TCXO -_ — 3.3V VDD (Max 4.0V))
F7VDDRF1V55PowerPower Supply Input (VDDRF1V55 — 3.3V VDD (Max 4.0V))
F8OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
G2PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
G3PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, I2C, PWM)
G4PB11I/OMultiplexed I/O & Peripheral Pin PB11 (PWM)
G5VSSGNDGround Reference Pin (VSS)
G6VSSRFGNDGround Reference Pin (VSSRF)
G7VSSRFGNDGround Reference Pin (VSSRF)
G8VSSRFGNDGround Reference Pin (VSSRF)
G9OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
H1PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, PWM)
H2PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART)
H3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, PWM)
H4PB10I/OMultiplexed I/O & Peripheral Pin PB10 (SPI, PWM)
H5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
H6VSSRFGNDGround Reference Pin (VSSRF)
H7RFI_NI/OMultiplexed I/O & Peripheral Pin RFI_N (General)
H8VDDPAPowerPower Supply Input (VDDPA — 3.3V VDD (Max 4.0V))
H9VR_PAI/OMultiplexed I/O & Peripheral Pin VR_PA (General)
J1PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI, RTC/CLK)
J2PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, PWM)
J3PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, SPI, RTC/CLK)
J5PH3BOOT0 -I/OMultiplexed I/O & Peripheral Pin PH3BOOT0 - (General)
J6RFI_PI/OMultiplexed I/O & Peripheral Pin RFI_P (General)
J8RFO_LPI/OMultiplexed I/O & Peripheral Pin RFO_LP (General)
J9RFO_HPI/OMultiplexed I/O & Peripheral Pin RFO_HP (General)
PIN A1 VSSSMPS
GND
Ground Reference Pin (VSSSMPS)
Design note: 0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32WLE4JCI6 (ST · UFBGA-73)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32WLE4JCI6 (UFBGA-73) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32WLE4JCI6 (UFBGA-73) - 2. Standard Pinout (Top View)
True package pinout (73 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32WLE4JCI6 (UFBGA-73) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32WLE4JCI6 (UFBGA-73) - 4. Package Dimensions (D×E×A)
UFBGA-73 · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32WLE4JCI6 (UFBGA-73) - 5. Recommended Land Pattern
IPC-7351B Footprint (73 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32WLE4JCI6 (UFBGA-73) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for STM32WLE4JCI / STM32WLE5CCU
P50 · p50_fig01EXACT PACKAGE
STM32WLE4JCI6 (UFBGA-73) — Figure 10. UFBGA73 pinout
Figure 10. UFBGA73 pinout
P138 · p138_fig01EXACT PACKAGE
STM32WLE4JCI6 (UFBGA-73) — Figure 33. UFBGA73 - Outline
Figure 33. UFBGA73 - Outline
P139 · p139_fig01EXACT PACKAGE
STM32WLE4JCI6 (UFBGA-73) — Figure 34. UFBGA73 - Recommended footprint
Figure 34. UFBGA73 - Recommended footprint
P140 · p140_fig01EXACT PACKAGE
STM32WLE4JCI6 (UFBGA-73) — Figure 35. UFBGA73 marking example (package top view)
Figure 35. UFBGA73 marking example (package top view)
P1 · p01_fig01881×564px
STM32WLE4JCI6 (UFBGA-73) — Multiprotocol LPWAN 32-bit Arm® Cortex®-M4 MCUs, LoRa®,
Multiprotocol LPWAN 32-bit Arm® Cortex®-M4 MCUs, LoRa®,
P49 · p49_fig011546×1065px
STM32WLE4JCI6 (UFBGA-73) — Figure 9. UFQFPN48 pinout
Figure 9. UFQFPN48 pinout
P50 · p50_fig01P50
STM32WLE4JCI6 (UFBGA-73) — Datasheet Page 50 (p50_fig01)
Datasheet Page 50 (p50_fig01)
P63 · p63_fig011546×1883px
STM32WLE4JCI6 (UFBGA-73) — Figure 13. Power supply scheme VBAT
Figure 13. Power supply scheme VBAT
P63 · p63_fig01P63
STM32WLE4JCI6 (UFBGA-73) — Datasheet Page 63 (p63_fig01)
Datasheet Page 63 (p63_fig01)
P98 · p98_fig011547×702px
STM32WLE4JCI6 (UFBGA-73) — Figure 16. Typical application with a 32.768 kHz crystal
Figure 16. Typical application with a 32.768 kHz crystal
P136 · p136_fig011546×1010px
STM32WLE4JCI6 (UFBGA-73) — Figure 31. UFQFPN48 - Recommended footprint
Figure 31. UFQFPN48 - Recommended footprint
P139 · p139_fig01P139
STM32WLE4JCI6 (UFBGA-73) — Datasheet Page 139 (p139_fig01)
Datasheet Page 139 (p139_fig01)
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (STM32WLE4JCI6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32WLE4JCI6 (UFBGA-73) is a 73-pin embedded microcontroller unit (mcu) featuring a 5.00 × 5.00 × 0.58 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8 V to 3.6 V supply operation across 40 °C to +105 °C with integrated UART, SPI, I2C, I2S, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
40 °C to +105 °C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
150 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
43 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.58 mm (A1=0.20 mm)
Package family: BGA (UFBGA-73)
Pin Count & Lead PitchN / e
73 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, I2S, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol73 auto-grouped pins
OK
IPC-7351B Land Pattern73 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — STM32WLE4JCI / STM32WLE5CCU (2)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (UFBGA-73)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.58mm · e=0.50mm
Pad Size (W × L)Level B
0.23 × 0.23 mm
Pins / Total PadsTopology
73P / 73Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-73
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32WLE4JCI6 (UFBGA-73)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32WLE4JCI6 (UFBGA-73)?

Manufactured by ST, the STM32WLE4JCI6 is housed in a UFBGA-73 package with 73 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.8 V to 3.6 V. Key pins include: A1 (VSSSMPS: Ground Reference Pin (VSSSMPS)), A2 (VDDSMPS: Power Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))), A4 (PA14: Multiplexed I/O & Peripheral Pin PA14 (I2C, ADC, SWD/JTAG)), A5 (VDDA: Power Supply Input (VDDA — 3.3V VDD (Max 4.0V))), A7 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), A8 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))).

What are the IPC-7351B PCB Footprint dimensions for STM32WLE4JCI6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32WLE4JCI6 (UFBGA-73) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 73 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32WLE4JCI6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32WLE4JCI6 (ST, UFBGA-73) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (73 pins) & STM32WLE4JCI / STM32WLE5CCU Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VSSSMPSGND0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
A2VDDSMPSPower_InPrimary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A4PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: I2C, ADC, SWD/JTAG.
A5VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A7VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A8VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A9PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: I2C, ADC.
B1VLXSMPSDigital_IOSignal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General.
B2VFBSMPSDigital_IOSignal terminal VFBSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VFBSMPS. Supported peripheral buses: General.
B3PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: I2C, ADC, SWD/JTAG.
B4PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, PWM.
B5VREF+AnalogSignal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
B6PC14OSC32 IN -_Digital_IOSignal terminal PC14OSC32 IN -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14OSC32 IN -_. Supported peripheral buses: RTC/CLK.
B7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B8PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SMBA. Supported peripheral buses: I2C, ADC, SWD/JTAG.
B9PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOUSART1CTS. Supported peripheral buses: SPI, ADC, PWM.
C1PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCKRFIRQ0. Supported peripheral buses: UART, SPI, ADC, SWD/JTAG.
C2PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA, SPI1_MISOUSART1CTS. Supported peripheral buses: SPI, I2C, SWD/JTAG.
C3PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: I2C.
C4PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI, PWM.
C5PC15 - OSC32_OUTDigital_IOSignal terminal PC15 - OSC32_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15 - OSC32_OUT. Supported peripheral buses: RTC/CLK.
C6PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: I2C, ADC, PWM.
C7PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
C8PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA, SPI2_MOSI. Supported peripheral buses: UART, SPI, I2C, DAC, RTC/CLK.
D2PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSIRFIRQ1. Supported peripheral buses: UART, SPI.
D3PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: PWM.
D4PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General.
D5PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI.
D6PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: PWM.
D7PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, ADC, PWM.
D8PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: SPI, ADC.
D9VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E1PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART.
E2VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E3VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E4PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General.
E5PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS, I2C1_SCL, SPI2_SCK. Supported peripheral buses: UART, SPI, I2C, PWM.
E6PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: UART, SPI.
E7PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART.
E8VDDRFPower_InPrimary positive power supply input (VDDRF) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E9VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F1PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, I2C.
F2PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General.
F3PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General.
F4PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOLPUART1CTS. Supported peripheral buses: SPI.
F5NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
F6PB0 VDD TCXO -_Power_OutRegulated power output rail (PB0 VDD TCXO -_) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F7VDDRF1V55Power_InPrimary positive power supply input (VDDRF1V55) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F8OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
G2PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
G3PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, I2C, PWM.
G4PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: PWM.
G5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
G6VSSRFGND0V electrical ground return terminal (VSSRF) for internal core logic, I/O drivers, and analog sub-blocks.
G7VSSRFGND0V electrical ground return terminal (VSSRF) for internal core logic, I/O drivers, and analog sub-blocks.
G8VSSRFGND0V electrical ground return terminal (VSSRF) for internal core logic, I/O drivers, and analog sub-blocks.
G9OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
H1PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, PWM.
H2PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART.
H3PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSICOMP2OUT. Supported peripheral buses: SPI, PWM.
H4PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: SPI, PWM.
H5VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
H6VSSRFGND0V electrical ground return terminal (VSSRF) for internal core logic, I/O drivers, and analog sub-blocks.
H7RFI_NRF_50OhmSignal terminal RFI_N (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: RFI_N. Supported peripheral buses: General.
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