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STM32F105VBH6TR (LFBGA-100) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F105VBH6TR

STID: C3207908LFBGA-100 · 100 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F105VBH6TR (LFBGA-100)A1PC14 - OSC32A2PC13TAMPER -A3PE2A4PB9A5PB7A6PB4A7PB3A8PA15A9PA14A10PA13B1PC15 - OSC32B2VBATB3PE3B4PB8B5PB6B6PD5B7PD2B8PC11B9PC10B10PA12C1OSC_INC2VSS_5C3PE4C4PE1C5PB5C6PD6C7PD3C8PC12C9PA9C10PA11D1OSC_OUTD2VDD_5D3PE5D4PE0D5BOOT0D6PD7D7PD4D8PD0D9PA8D10PA10E1NRSTE2PC2E3PE6E4VSS_4E5VSS_3E6VSS_2E7VSS_1E8PD1E9PC9E10PC7K10PD12K9PD8K8PB12K7PB11K6PE13K5PE9K4PB1K3PA7K2PA3K1VDDAJ10PD13J9PD9J8PB13J7PB10J6PE12J5PE8J4PB0J3PA6J2PA2J1VREF+H10PD14H9PD10H8PB14H7PE15H6PE11H5PE7H4PC5H3PA5H2PA1H1VREF-G10PD15G9PD11G8PB15G7PE14G6PE10G5PB2G4PC4G3PA4G2PA0WKUP -G1VSSAF10PC6F9PC8F8NotconnectedF7VDD_1F6VDD_2F5VDD_3F4VDD_4F3PC3F2PC1F1PC0Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1K1A2B2C2D2E2F2G2H2J2K2A3B3C3D3E3F3G3H3J3K3A4B4C4D4E4F4G4H4J4K4A5B5C5D5E5F5G5H5J5K5A6B6C6D6E6F6G6H6J6K6A7B7C7D7E7F7G7H7J7K7A8B8C8D8E8F8G8H8J8K8A9B9C9D9E9F9G9H9J9K9A10B10C10D10E10F10G10H10J10K10E=10.00mm · Pitch e=0.80mmD=10.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PC14 - OSC32 IN(5)_I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32 IN(5)_ (RTC/CLK)
A2PC13TAMPER - - RTCI/OMultiplexed I/O & Peripheral Pin PC13TAMPER - - RTC (RTC/CLK)
A3PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
A4PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
A5PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C)
A6PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI, SWD/JTAG)
A7PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SPI, SWD/JTAG)
A8PA15I/OMultiplexed I/O & Peripheral Pin PA15 (SPI, SWD/JTAG)
A9PA14I/OMultiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
A10PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
B1PC15 - OSC32 OUT(5)_I/OMultiplexed I/O & Peripheral Pin PC15 - OSC32 OUT(5)_ (RTC/CLK)
B2VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
B3PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
B4PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
B5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C)
B6PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
B7PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
B8PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART)
B9PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART)
B10PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART, CAN)
C1OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
C2VSS_5GNDGround Reference Pin (VSS_5)
C3PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
C4PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
C5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C)
C6PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
C7PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
C8PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART)
C9PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART)
C10PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, CAN)
D1OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
D2VDD_5PowerPower Supply Input (VDD_5 — 3.3V VDD (Max 4.0V))
D3PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
D4PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
D5BOOT0IInput-Only Pin BOOT0 (General)
D6PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
D7PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
D8PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
D9PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, RTC/CLK)
D10PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART)
E1NRSTISystem Enable & Hardware Reset (NRST)
E2PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
E3PE6I/OMultiplexed I/O & Peripheral Pin PE6 (General)
E4VSS_4GNDGround Reference Pin (VSS_4)
E5VSS_3GNDGround Reference Pin (VSS_3)
E6VSS_2GNDGround Reference Pin (VSS_2)
E7VSS_1GNDGround Reference Pin (VSS_1)
E8PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
E9PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
E10PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
F1PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
F2PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
F3PC3I/OMultiplexed I/O & Peripheral Pin PC3 (ADC)
F4VDD_4PowerPower Supply Input (VDD_4 — 3.3V VDD (Max 4.0V))
F5VDD_3PowerPower Supply Input (VDD_3 — 3.3V VDD (Max 4.0V))
F6VDD_2PowerPower Supply Input (VDD_2 — 3.3V VDD (Max 4.0V))
F7VDD_1PowerPower Supply Input (VDD_1 — 3.3V VDD (Max 4.0V))
F8NotconnectedI/OMultiplexed I/O & Peripheral Pin Notconnected (General)
F9PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
F10PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
G1VSSAGNDGround Reference Pin (VSSA)
G2PA0WKUP -I/OMultiplexed I/O & Peripheral Pin PA0WKUP - (UART, ADC, PWM)
G3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI, DAC)
G4PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART, ADC)
G5PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
G6PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
G7PE14I/OMultiplexed I/O & Peripheral Pin PE14 (General)
G8PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI)
G9PD11I/OMultiplexed I/O & Peripheral Pin PD11 (General)
G10PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
H1VREF-AnalogMultiplexed I/O & Peripheral Pin VREF- (General)
H2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC)
H3PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC)
H4PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART, ADC)
H5PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
H6PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
H7PE15I/OMultiplexed I/O & Peripheral Pin PE15 (General)
H8PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI)
H9PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
H10PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
J1VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
J2PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC)
J3PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
J4PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, ADC)
J5PE8I/OMultiplexed I/O & Peripheral Pin PE8 (General)
J6PE12I/OMultiplexed I/O & Peripheral Pin PE12 (General)
J7PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, I2C)
J8PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, CAN)
J9PD9I/OMultiplexed I/O & Peripheral Pin PD9 (General)
J10PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
K1VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
K2PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC)
K3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC)
K4PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC)
K5PE9I/OMultiplexed I/O & Peripheral Pin PE9 (General)
K6PE13I/OMultiplexed I/O & Peripheral Pin PE13 (General)
K7PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C)
K8PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C, CAN)
K9PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
K10PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
PIN A1 PC14 - OSC32 IN(5)_
I/O
Multiplexed I/O & Peripheral Pin PC14 - OSC32 IN(5)_ (RTC/CLK)
Design note: PC14(6) | Alt: OSC32_IN
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 18 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F105VBH6TR (ST · LFBGA-100)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F105VBH6TR (LFBGA-100) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F105VBH6TR (LFBGA-100) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F105VBH6TR (LFBGA-100) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F105VBH6TR (LFBGA-100) - 4. Package Dimensions (D×E×A)
LFBGA-100 · 10.00×10.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F105VBH6TR (LFBGA-100) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F105VBH6TR (LFBGA-100) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (18 figures · Page 1/2)
Showing 1–12 of 18 uncropped original figures for STM32F105 / STM32F107
P24 · p24_fig01EXACT PACKAGE
STM32F105VBH6TR (LFBGA-100) — Figure 2. STM32F105xx and STM32F107xx connectivity line BGA100 ballout top view 8 7 6 5 4 3 2 1
Figure 2. STM32F105xx and STM32F107xx connectivity line BGA100 ballout top view 8 7 6 5 4 3 2 1
P78 · p78_fig01EXACT PACKAGE
STM32F105VBH6TR (LFBGA-100) — Figure 36. Power supply and reference decoupling (VREF+ not connected to VDDA)
Figure 36. Power supply and reference decoupling (VREF+ not connected to VDDA)
P78 · p78_fig02EXACT PACKAGE
STM32F105VBH6TR (LFBGA-100) — Figure 37. Power supply and reference decoupling (VREF+ connected to VDDA)
Figure 37. Power supply and reference decoupling (VREF+ connected to VDDA)
P82 · p82_fig01EXACT PACKAGE
STM32F105VBH6TR (LFBGA-100) — Figure 39. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
Figure 39. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
P83 · p83_fig01EXACT PACKAGE
STM32F105VBH6TR (LFBGA-100) — Figure 41. LFBGA100 - 100-ball low profile fine pitch ball grid array, 10 x 10 mm,
Figure 41. LFBGA100 - 100-ball low profile fine pitch ball grid array, 10 x 10 mm,
P85 · p85_fig01EXACT PACKAGE
STM32F105VBH6TR (LFBGA-100) — Figure 43. LQFP100 - 14 x 14 mm 100 pin low-profile quad flat package outline 3%!4).'�0,!.%
Figure 43. LQFP100 - 14 x 14 mm 100 pin low-profile quad flat package outline 3%!4).'0,!.%
P86 · p86_fig01EXACT PACKAGE
STM32F105VBH6TR (LFBGA-100) — Figure 44. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
Figure 44. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
P107 · p107_fig01EXACT PACKAGE
STM32F105VBH6TR (LFBGA-100) — STM32F105xx, STM32F107xx Revision history
STM32F105xx, STM32F107xx Revision history
P1 · p01_fig01881×420px
STM32F105VBH6TR (LFBGA-100) — • Memories - 64 to 256 Kbytes of Flash memory - 64 Kbytes of general-purpose SRAM
• Memories - 64 to 256 Kbytes of Flash memory - 64 Kbytes of general-purpose SRAM
P35 · p35_fig011546×1313px
STM32F105VBH6TR (LFBGA-100) — Figure 8. Power supply scheme 9%$7
Figure 8. Power supply scheme 9%$7
P35 · p35_fig021875×919px
STM32F105VBH6TR (LFBGA-100) — Figure 9. Current consumption measurement scheme
Figure 9. Current consumption measurement scheme
P35 · p35_fig01P35
STM32F105VBH6TR (LFBGA-100) — Datasheet Page 35 (p35_fig01)
Datasheet Page 35 (p35_fig01)
Page 1 / 2 (18 extracted figures)

Technical Specifications & Part Details (STM32F105VBH6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F105VBH6TR (LFBGA-100) is a 100-pin embedded microcontroller unit (mcu) featuring a 10.00 × 10.00 × 1.35 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
72 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.35 mm (A1=0.27 mm)
Package family: BGA (LFBGA-100)
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0, PB2): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — STM32F105 / STM32F107 (12)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (LFBGA-100)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.35mm · e=0.80mm
Pad Size (W × L)Level B
0.40 × 0.40 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LFBGA-100
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F105VBH6TR (LFBGA-100)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F105VBH6TR (LFBGA-100)?

Manufactured by ST, the STM32F105VBH6TR is housed in a LFBGA-100 package with 100 pins and a 0.80 mm lead pitch. Key pins include: A1 (PC14 - OSC32 IN(5)_: Multiplexed I/O & Peripheral Pin PC14 - OSC32 IN(5)_ (RTC/CLK)), A2 (PC13TAMPER - - RTC: Multiplexed I/O & Peripheral Pin PC13TAMPER - - RTC (RTC/CLK)), A3 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), A4 (PB9: Multiplexed I/O & Peripheral Pin PB9 (General)), A5 (PB7: Multiplexed I/O & Peripheral Pin PB7 (I2C)), A6 (PB4: Multiplexed I/O & Peripheral Pin PB4 (SPI, SWD/JTAG)).

What are the IPC-7351B PCB Footprint dimensions for STM32F105VBH6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F105VBH6TR (LFBGA-100) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.80 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F105VBH6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F105VBH6TR (ST, LFBGA-100) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32F105 / STM32F107 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PC14 - OSC32 IN(5)_Digital_IOSignal terminal PC14 - OSC32 IN(5)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14 - OSC32 IN(5)_. Supported peripheral buses: RTC/CLK.
A2PC13TAMPER - - RTCDigital_IOSignal terminal PC13TAMPER - - RTC (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13TAMPER - - RTC. Supported peripheral buses: RTC/CLK.
A3PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
A4PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
A5PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: I2C.
A6PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: SPI, SWD/JTAG.
A7PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: SPI, SWD/JTAG.
A8PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_NSS. Supported peripheral buses: SPI, SWD/JTAG.
A9PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: SWD/JTAG.
A10PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
B1PC15 - OSC32 OUT(5)_Digital_IOSignal terminal PC15 - OSC32 OUT(5)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15 - OSC32 OUT(5)_. Supported peripheral buses: RTC/CLK.
B2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B3PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
B4PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
B5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
B6PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
B7PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
B8PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: UART.
B9PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: UART.
B10PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART, CAN.
C1OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
C2VSS_5GND0V electrical ground return terminal (VSS_5) for internal core logic, I/O drivers, and analog sub-blocks.
C3PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
C4PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
C5PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SMBA, SPI3_MOSI. Supported peripheral buses: SPI, I2C.
C6PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
C7PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
C8PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: UART.
C9PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART.
C10PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: UART, CAN.
D1OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
D2VDD_5Power_InPrimary positive power supply input (VDD_5) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D3PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
D4PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
D5BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
D6PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
D7PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
D8PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
D9PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, RTC/CLK.
D10PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART.
E1NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
E2PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: ADC.
E3PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
E4VSS_4GND0V electrical ground return terminal (VSS_4) for internal core logic, I/O drivers, and analog sub-blocks.
E5VSS_3GND0V electrical ground return terminal (VSS_3) for internal core logic, I/O drivers, and analog sub-blocks.
E6VSS_2GND0V electrical ground return terminal (VSS_2) for internal core logic, I/O drivers, and analog sub-blocks.
E7VSS_1GND0V electrical ground return terminal (VSS_1) for internal core logic, I/O drivers, and analog sub-blocks.
E8PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
E9PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
E10PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
F1PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
F2PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: ADC.
F3PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: ADC.
F4VDD_4Power_InPrimary positive power supply input (VDD_4) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F5VDD_3Power_InPrimary positive power supply input (VDD_3) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F6VDD_2Power_InPrimary positive power supply input (VDD_2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F7VDD_1Power_InPrimary positive power supply input (VDD_1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F8NotconnectedDigital_IOSignal terminal Notconnected (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: Notconnected. Supported peripheral buses: General.
F9PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
F10PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
G1VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
G2PA0WKUP -Digital_IOSignal terminal PA0WKUP - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0WKUP -. Supported peripheral buses: UART, ADC, PWM.
G3PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: SPI, DAC.
G4PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: UART, ADC.
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