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CH567L (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH567L

WCHID: C3036275LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH567L (LQFP-48(7x7))1PA12PA03V33IO14PB75PB66PB57PB48PB39PB210PB111PB012RUSB013UDP014UDM015V33USB16XO17XI18RUSB119UDP120UDM121V33IO322GND23VCORE24PB1148PA247PA1246PA1345PA1444PA1543VCORE42GND41V33REG40PA939V33IO238PA1137PA1036PA835PA734PA633PA532PA431PA330RST#29PB1028PB927PB826PB1325PB12Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.235.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PA1I/OMultiplexed I/O & Peripheral Pin PA1 (SPI)
2PA0I/OMultiplexed I/O & Peripheral Pin PA0 (SPI)
3V33IO1PowerPower Supply Input (V33IO1 — 3.3V / 5.0V Standard Logic)
4PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
6PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
7PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
8PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
9PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
10PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
11PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
12RUSB0I/OMultiplexed I/O & Peripheral Pin RUSB0 (General)
13UDP0I/OMultiplexed I/O & Peripheral Pin UDP0 (General)
14UDM0I/OMultiplexed I/O & Peripheral Pin UDM0 (General)
15V33USBPowerPower Supply Input (V33USB — 3.3V / 5.0V Standard Logic)
16XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
17XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
18RUSB1I/OMultiplexed I/O & Peripheral Pin RUSB1 (General)
19UDP1I/OMultiplexed I/O & Peripheral Pin UDP1 (General)
20UDM1I/OMultiplexed I/O & Peripheral Pin UDM1 (General)
21V33IO3PowerPower Supply Input (V33IO3 — 3.3V / 5.0V Standard Logic)
22GNDGNDGround Reference Pin (GND)
23VCOREI/OMultiplexed I/O & Peripheral Pin VCORE (General)
24PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
25PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
26PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
27PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
28PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
29PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
30RST#I/OMultiplexed I/O & Peripheral Pin RST# (General)
31PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
32PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
33PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
34PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
35PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
36PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
37PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
38PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
39V33IO2PowerPower Supply Input (V33IO2 — 3.3V / 5.0V Standard Logic)
40PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
41V33REGPowerPower Supply Input (V33REG — 3.3V / 5.0V Standard Logic)
42GNDGNDGround Reference Pin (GND)
43VCOREI/OMultiplexed I/O & Peripheral Pin VCORE (General)
44PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
45PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
46PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
47PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
48PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
PIN 1 PA1
I/O
Multiplexed I/O & Peripheral Pin PA1 (SPI)
Design note: PA1:General purposebidirectionaldigitalI/Opin . MOSI1:SPI1serialdatapin hostoutput , . LED1:LEDserialdataline1 . CMD2:SD2controllercommandsignalline . A1:Parallelportaddressline1 .
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH567L (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH567L (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH567L (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH567L (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH567L (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH567L (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH567L (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH567
P2 · p02_fig01EXACT PACKAGE
CH567L (LQFP-48(7x7)) — Figure 2-1 LQFP48 Package Pin Arrangement 1.2 Pin Description
Figure 2-1 LQFP48 Package Pin Arrangement 1.2 Pin Description
P1 · p01_fig01286×191px
CH567L (LQFP-48(7x7)) — Overview
Overview
P2 · p02_fig01P2
CH567L (LQFP-48(7x7)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P6 · p06_fig011771×665px
CH567L (LQFP-48(7x7)) — CH567 Datasheet 5 http://wch.cn
CH567 Datasheet 5 http://wch.cn
P10 · p10_fig011277×515px
CH567L (LQFP-48(7x7)) — easier gat Voc ; Tero oo TIME-OUT . INTERNW AL RESET
easier gat Voc ; Tero oo TIME-OUT . INTERNW AL RESET
P96 · p96_fig011657×1208px
CH567L (LQFP-48(7x7)) — The unit of dimension is mm (millimeters) The pin center spacing is the nominal value, there is no error, and the other dimension error is not greater than ±0.5mm.
The unit of dimension is mm (millimeters) The pin center spacing is the nominal value, there is no error, and the other dimension error is not greater than ±0.5mm.

Technical Specifications & Part Details (CH567L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH567L (LQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, PWM, SDIO, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
120MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, PWM, SDIO, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH567L (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH567L (LQFP-48(7x7))?

Manufactured by WCH, the CH567L is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (PA1: Multiplexed I/O & Peripheral Pin PA1 (SPI)), 2 (PA0: Multiplexed I/O & Peripheral Pin PA0 (SPI)), 3 (V33IO1: Power Supply Input (V33IO1 — 3.3V / 5.0V Standard Logic)), 4 (PB7: Multiplexed I/O & Peripheral Pin PB7 (General)), 5 (PB6: Multiplexed I/O & Peripheral Pin PB6 (General)), 6 (PB5: Multiplexed I/O & Peripheral Pin PB5 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH567L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH567L (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH567L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH567L (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH567 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1SERIALDATAPIN. Supported peripheral buses: SPI.
2PA0Digital_IOSignal terminal PA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1SERIALCLOCKPIN. Supported peripheral buses: SPI.
3V33IO1Power_InPrimary positive power supply input (V33IO1) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
6PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
7PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
8PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
9PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
10PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
11PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
12RUSB0Digital_IOSignal terminal RUSB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RUSB0. Supported peripheral buses: General.
13UDP0Digital_IOSignal terminal UDP0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UDP0. Supported peripheral buses: General.
14UDM0Digital_IOSignal terminal UDM0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UDM0. Supported peripheral buses: General.
15V33USBPower_InPrimary positive power supply input (V33USB) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
16XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
17XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
18RUSB1Digital_IOSignal terminal RUSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RUSB1. Supported peripheral buses: General.
19UDP1Digital_IOSignal terminal UDP1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UDP1. Supported peripheral buses: General.
20UDM1Digital_IOSignal terminal UDM1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UDM1. Supported peripheral buses: General.
21V33IO3Power_InPrimary positive power supply input (V33IO3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
22GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
23VCOREDigital_IOSignal terminal VCORE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCORE. Supported peripheral buses: General.
24PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
25PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
26PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
27PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
28PB9Digital_IOSignal terminal PB9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
29PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
30RST#Digital_IOSignal terminal RST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST#. Supported peripheral buses: General.
31PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
32PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
33PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
34PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
35PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
36PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
37PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
38PA11Digital_IOSignal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
39V33IO2Power_InPrimary positive power supply input (V33IO2) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
40PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
41V33REGPower_InPrimary positive power supply input (V33REG) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
42GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
43VCOREDigital_IOSignal terminal VCORE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCORE. Supported peripheral buses: General.
44PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
45PA14Digital_IOSignal terminal PA14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
46PA13Digital_IOSignal terminal PA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
47PA12Digital_IOSignal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
48PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
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