SMD · 14P
Synchronized Pinout (Symbol / 2D / 3D) (14/14)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | IO3 | I/O | Multiplexed I/O & Peripheral Pin IO3 (ADC) |
| 2 | IO7 | I/O | Multiplexed I/O & Peripheral Pin IO7 (SPI, SWD/JTAG) |
| 3 | IO6 | I/O | Multiplexed I/O & Peripheral Pin IO6 (SPI, SWD/JTAG) |
| 4 | IO4 | I/O | Multiplexed I/O & Peripheral Pin IO4 (SPI, ADC, SWD/JTAG) |
| 5 | IO5 | I/O | Multiplexed I/O & Peripheral Pin IO5 (SPI, ADC, SWD/JTAG) |
| 6 | GND | GND | Ground Reference Pin (GND) |
| 7 | 3V3 | Power | Power Supply Input (3V3 — 3.0 ~ 3.6 V) |
| 8 | GND | GND | Ground Reference Pin (GND) |
| 9 | 3V3 | Power | Power Supply Input (3V3 — 3.0 ~ 3.6 V) |
| 10 | RX | I/O | Multiplexed I/O & Peripheral Pin RX (UART) |
| 11 | TX | I/O | Multiplexed I/O & Peripheral Pin TX (UART) |
| 12 | IO9 | I/O | Multiplexed I/O & Peripheral Pin IO9 (General) |
| 13 | EN | I | System Enable & Hardware Reset (EN) |
| 14 | GND | GND | Ground Reference Pin (GND) |
PIN 1 IO3
I/OMultiplexed I/O & Peripheral Pin IO3 (ADC)
Design note: GPIO3 ADC1 CH3 LEDPWM ,_ ,
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (14 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SMD · 15.00×17.30mm · Pitch 2.00mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (22 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for ESP8685-WROOM
P1 · p01_fig01EXACT PACKAGE
P22 · p22_fig01EXACT PACKAGE
P1 · p01_fig02646×314px
P1 · p01_fig01P1
P9 · p09_fig01647×514px
P9 · p09_fig01P9
P11 · p11_fig01873×717px
P22 · p22_fig01P22
P23 · p23_fig01745×508px
P23 · p23_fig02654×607px
P23 · p23_fig02P23
P24 · p24_fig011098×957px
Page 1 / 2 (13 extracted figures)
Technical Specifications & Part Details (ESP8685-WROOM-05-H2)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:ESP8685-WROOM-05-H2 (SMD) is a 14-pin wireless wi-fi / bluetooth le soc module featuring a 17.30 × 15.00 × 2.40 mm mechanical envelope (lead pitch e = 2.00 mm). Rated for 3.0 ~ 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Wi-Fi, Bluetooth / BLE, USB, UART, SPI, I2C, I2S, PWM, JTAG / SWD, ADC, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0 ~ 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
17.30 × 15.00 × 2.40 mm (A1=0.00 mm)
Package family: CASTELLATED_MODULE (SMD)
Pin Count & Lead PitchN / e
14 Pins | Pitch e = 2.00 mm (78.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, Bluetooth / BLE, USB, UART, SPI, I2C, I2S, PWM, JTAG / SWD, ADC, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol14 auto-grouped pins
IPC-7351B Land Pattern22 pads · Pitch 2.00mm
IPC-7525 60% Solder PasteEPAD 3.96×3.19mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — ESP8685-WROOM (2)
SMD · 23P
Mechanical Dimensions & Land Pattern (SMD)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
17.30 × 15.00 mm
Height (A) & Pitch (e)IPC-7351B
A=2.40mm · e=2.00mm
Pad Size (W × L)Level B
1.20 × 2.08 mm
Pins / Total PadsTopology
14P / 22Pad (CASTELLATED_MODULE)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit SMD | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — ESP8685-WROOM-05-H2 (SMD)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of ESP8685-WROOM-05-H2 (SMD)?
Manufactured by ESPRESSIF, the ESP8685-WROOM-05-H2 is housed in a SMD package with 14 pins and a 2.00 mm lead pitch, supporting a VCC supply range of 3.0 ~ 3.6 V. Key pins include: 1 (IO3: Multiplexed I/O & Peripheral Pin IO3 (ADC)), 2 (IO7: Multiplexed I/O & Peripheral Pin IO7 (SPI, SWD/JTAG)), 3 (IO6: Multiplexed I/O & Peripheral Pin IO6 (SPI, SWD/JTAG)), 4 (IO4: Multiplexed I/O & Peripheral Pin IO4 (SPI, ADC, SWD/JTAG)), 5 (IO5: Multiplexed I/O & Peripheral Pin IO5 (SPI, ADC, SWD/JTAG)), 6 (GND: Ground Reference Pin (GND)).
What are the IPC-7351B PCB Footprint dimensions for ESP8685-WROOM-05-H2?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ESP8685-WROOM-05-H2 (SMD) has a nominal body envelope of 15.00 × 17.30 mm, pitch e = 2.00 mm, and 22 copper pads plus a central exposed thermal pad (EPAD) of 3.96 × 3.19 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ESP8685-WROOM-05-H2?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ESP8685-WROOM-05-H2 (ESPRESSIF, SMD) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (14 pins) & ESP8685-WROOM Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | IO3 | Digital_IO | Signal terminal IO3 (I/O, 3.0 ~ 3.6 V domain). Multiplexed alternate functions: GPIO3, ADC1_CH3. Supported peripheral buses: ADC. |
| 2 | IO7 | Digital_IO | Signal terminal IO7 (I/O, 3.0 ~ 3.6 V domain). Multiplexed alternate functions: GPIO7, FSPID, MTDO. Supported peripheral buses: SPI, SWD/JTAG. |
| 3 | IO6 | Digital_IO | Signal terminal IO6 (I/O, 3.0 ~ 3.6 V domain). Multiplexed alternate functions: GPIO6, FSPICLK, MTCK. Supported peripheral buses: SPI, SWD/JTAG. |
| 4 | IO4 | Digital_IO | Signal terminal IO4 (I/O, 3.0 ~ 3.6 V domain). Multiplexed alternate functions: GPIO4, ADC1_CH4, FSPIHD, MTMS. Supported peripheral buses: SPI, ADC, SWD/JTAG. |
| 5 | IO5 | Digital_IO | Signal terminal IO5 (I/O, 3.0 ~ 3.6 V domain). Multiplexed alternate functions: GPIO5, ADC2_CH0, FSPIWP, MTDI. Supported peripheral buses: SPI, ADC, SWD/JTAG. |
| 6 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 7 | 3V3 | Power_In | Primary positive power supply input (3V3) operating in the 3.0 ~ 3.6 V domain (Max rating: 3.6V). |
| 8 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 9 | 3V3 | Power_In | Primary positive power supply input (3V3) operating in the 3.0 ~ 3.6 V domain (Max rating: 3.6V). |
| 10 | RX | Digital_IO | Signal terminal RX (I/O, 3.0 ~ 3.6 V domain). Multiplexed alternate functions: GPIO20, U0RXD. Supported peripheral buses: UART. |
| 11 | TX | Digital_IO | Signal terminal TX (I/O, 3.0 ~ 3.6 V domain). Multiplexed alternate functions: GPIO21, U0TXD. Supported peripheral buses: UART. |
| 12 | IO9 | Digital_IO | Signal terminal IO9 (I/O, 3.0 ~ 3.6 V domain). Multiplexed alternate functions: GPIO9. Supported peripheral buses: General. |
| 13 | EN | Digital_IO | Chip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset. |
| 14 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |