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ESP8685-WROOM-01-H2 (SMD) — Symbol, Footprint IPC-7351B & 3D STEP Model

ESP8685-WROOM-01-H2

ESPRESSIFID: C3013924SMD · 23 Pins · Pitch 2.00mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ESP8685-WROOM-01-H2 (SMD)1IO02IO13EN4IO25IO46IO57IO683V39IO1810IO1911NC12NC23GND22TXD021RXD020IO319IO1018IO917IO816IO715GND14NC13NCGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.820.315.210.25.10-5.1-10.2-15.2-20.3mm
2. 2D FOOTPRINT
ANTENNA KEEPOUT (7.6mm)12345679101112131415161718192021228232323232323232323E=16.00mm · Pitch e=2.00mmD=24.00mm-15-13-11-9-7-5-3-113579111315191715131197531-1-3-5-7-9-11-13-15-17-19mm
3. 3D CAD MODEL
Package Body: 16.00mm × 24.00mm · Pitch: 2.00mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (23/23)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1IO0I/OMultiplexed I/O & Peripheral Pin IO0 (General)
2IO1I/OMultiplexed I/O & Peripheral Pin IO1 (General)
3ENISystem Enable & Hardware Reset (EN)
4IO2I/OMultiplexed I/O & Peripheral Pin IO2 (General)
5IO4I/OMultiplexed I/O & Peripheral Pin IO4 (General)
6IO5I/OMultiplexed I/O & Peripheral Pin IO5 (General)
7IO6I/OMultiplexed I/O & Peripheral Pin IO6 (General)
83V3PowerPower Supply Input (3V3 — 3.3V / 5.0V Standard Logic)
9IO18I/OMultiplexed I/O & Peripheral Pin IO18 (General)
10IO19I/OMultiplexed I/O & Peripheral Pin IO19 (General)
11NCI/OMultiplexed I/O & Peripheral Pin NC (General)
12NCI/OMultiplexed I/O & Peripheral Pin NC (General)
13NCI/OMultiplexed I/O & Peripheral Pin NC (General)
14NCI/OMultiplexed I/O & Peripheral Pin NC (General)
15GNDGNDGround Reference Pin (GND)
16IO7I/OMultiplexed I/O & Peripheral Pin IO7 (General)
17IO8I/OMultiplexed I/O & Peripheral Pin IO8 (General)
18IO9I/OMultiplexed I/O & Peripheral Pin IO9 (General)
19IO10I/OMultiplexed I/O & Peripheral Pin IO10 (General)
20IO3I/OMultiplexed I/O & Peripheral Pin IO3 (General)
21RXD0I/OMultiplexed I/O & Peripheral Pin RXD0 (UART)
22TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
23GNDGNDGround Reference Pin (GND)
PIN 1 IO0
I/O
Multiplexed I/O & Peripheral Pin IO0 (General)
Design note: Signal terminal IO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO0. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ESP8685-WROOM-01-H2 (ESPRESSIF · SMD)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ESP8685-WROOM-01-H2 (SMD) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ESP8685-WROOM-01-H2 (SMD) - 2. Standard Pinout (Top View)
True package pinout (23 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ESP8685-WROOM-01-H2 (SMD) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ESP8685-WROOM-01-H2 (SMD) - 4. Package Dimensions (D×E×A)
SMD · 16.00×24.00mm · Pitch 2.00mmExpand ›
5. Recommended Land PatternLAND PATTERN
ESP8685-WROOM-01-H2 (SMD) - 5. Recommended Land Pattern
IPC-7351B Footprint (31 Pads)Expand ›
6. Application SchematicSCHEMATIC
ESP8685-WROOM-01-H2 (SMD) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (ESP8685-WROOM-01-H2)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Wireless Wi-Fi / Bluetooth LE SoC Module
Detailed Overview:ESP8685-WROOM-01-H2 (SMD) is a 22-pin wireless wi-fi / bluetooth le soc module featuring a 24.00 × 16.00 × 2.40 mm mechanical envelope (lead pitch e = 2.00 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
24.00 × 16.00 × 2.40 mm (A1=0.00 mm)
Package family: CASTELLATED_MODULE (SMD)
Pin Count & Lead PitchN / e
22 Pins | Pitch e = 2.00 mm (78.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol23 auto-grouped pins
OK
IPC-7351B Land Pattern31 pads · Pitch 2.00mm
OK
IPC-7525 60% Solder PasteEPAD 2.80×2.80mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SMD)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
24.00 × 16.00 mm
Height (A) & Pitch (e)IPC-7351B
A=2.40mm · e=2.00mm
Pad Size (W × L)Level B
1.10 × 2.40 mm
Pins / Total PadsTopology
23P / 31Pad (CASTELLATED_MODULE)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SMD
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ESP8685-WROOM-01-H2 (SMD)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ESP8685-WROOM-01-H2 (SMD)?

Manufactured by ESPRESSIF, the ESP8685-WROOM-01-H2 is housed in a SMD package with 23 pins and a 2.00 mm lead pitch. Key pins include: 1 (IO0: Multiplexed I/O & Peripheral Pin IO0 (General)), 2 (IO1: Multiplexed I/O & Peripheral Pin IO1 (General)), 3 (EN: System Enable & Hardware Reset (EN)), 4 (IO2: Multiplexed I/O & Peripheral Pin IO2 (General)), 5 (IO4: Multiplexed I/O & Peripheral Pin IO4 (General)), 6 (IO5: Multiplexed I/O & Peripheral Pin IO5 (General)).

What are the IPC-7351B PCB Footprint dimensions for ESP8685-WROOM-01-H2?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ESP8685-WROOM-01-H2 (SMD) has a nominal body envelope of 16.00 × 24.00 mm, pitch e = 2.00 mm, and 31 copper pads plus a central exposed thermal pad (EPAD) of 2.80 × 2.80 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ESP8685-WROOM-01-H2?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ESP8685-WROOM-01-H2 (ESPRESSIF, SMD) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (23 pins) & ESP8685-WROOM Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1IO0Digital_IOSignal terminal IO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO0. Supported peripheral buses: General.
2IO1Digital_IOSignal terminal IO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO1. Supported peripheral buses: General.
3ENDigital_IOChip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset.
4IO2Digital_IOSignal terminal IO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO2. Supported peripheral buses: General.
5IO4Digital_IOSignal terminal IO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO4. Supported peripheral buses: General.
6IO5Digital_IOSignal terminal IO5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO5. Supported peripheral buses: General.
7IO6Digital_IOSignal terminal IO6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO6. Supported peripheral buses: General.
83V3Power_InPrimary positive power supply input (3V3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
9IO18Digital_IOSignal terminal IO18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO18. Supported peripheral buses: General.
10IO19Digital_IOSignal terminal IO19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO19. Supported peripheral buses: General.
11NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
12NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
13NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
14NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
15GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
16IO7Digital_IOSignal terminal IO7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO7. Supported peripheral buses: General.
17IO8Digital_IOSignal terminal IO8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO8. Supported peripheral buses: General.
18IO9Digital_IOSignal terminal IO9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO9. Supported peripheral buses: General.
19IO10Digital_IOSignal terminal IO10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO10. Supported peripheral buses: General.
20IO3Digital_IOSignal terminal IO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO3. Supported peripheral buses: General.
21RXD0Digital_IOSignal terminal RXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD0. Supported peripheral buses: UART.
22TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
23GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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