Mechanical Dimensions & Land Pattern (SSOP-10_L5.0-W3.9-P1.00-LS6.0-BL-EP)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit SSOP-10_L5.0-W3.9-P1.00-LS6.0-BL-EP | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — C3001173 (SSOP-10_L5.0-W3.9-P1.00-LS6.0-BL-EP)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of C3001173 (SSOP-10_L5.0-W3.9-P1.00-LS6.0-BL-EP)?
Manufactured by Semiconductor, the C3001173 is housed in a SSOP-10_L5.0-W3.9-P1.00-LS6.0-BL-EP package with 11 pins and a 1.00 mm lead pitch. Key pins include: 1 (SLEEP: Multiplexed I/O & Peripheral Pin SLEEP (General)), 2 (VCC: Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)), 3 (GND: Ground Reference Pin (GND)), 4 (X32MI: Multiplexed I/O & Peripheral Pin X32MI (General)), 5 (X32MO: Multiplexed I/O & Peripheral Pin X32MO (General)), 6 (ANT: Multiplexed I/O & Peripheral Pin ANT (General)).
What are the IPC-7351B PCB Footprint dimensions for C3001173?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C3001173 (SSOP-10_L5.0-W3.9-P1.00-LS6.0-BL-EP) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 1.00 mm, and 11 copper pads plus a central exposed thermal pad (EPAD) of 2.42 × 3.17 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C3001173?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C3001173 (Semiconductor, SSOP-10_L5.0-W3.9-P1.00-LS6.0-BL-EP) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (11 pins) & CH9141 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | SLEEP | Digital_IO | Signal terminal SLEEP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SLEEP. Supported peripheral buses: General. |
| 2 | VCC | Power_In | Primary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 3 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 4 | X32MI | Digital_IO | Signal terminal X32MI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MI. Supported peripheral buses: General. |
| 5 | X32MO | Digital_IO | Signal terminal X32MO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MO. Supported peripheral buses: General. |
| 6 | ANT | Digital_IO | Signal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General. |
| 7 | VINTA | Power_In | Primary positive power supply input (VINTA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 8 | RXD | Digital_IO | Signal terminal RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART. |
| 9 | TXD | Digital_IO | Signal terminal TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART. |
| 10 | AT | Digital_IO | Signal terminal AT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AT. Supported peripheral buses: General. |
| 11 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |