ChipDocs.org
⌘K
2284 PARTSUpload PDF
CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH582M-EVT

WCHID: C2943981QFN-48_L5.0-W5.0-P0.35-BL-EP · 49 Pins · Pitch 0.35mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP)1VDCID2VSW3VDD33/VIO334PA75PA86PA97PB98PB89PB1710PB1611PB1512PB1413PB1314PB1215PB1116PB1017PB718PB619PB520PB421PB322PB223PB124PB025PB2349EP48PA1047PA1146PA1245PA1344PA1443PA1542PA341PA240PA139PA038PA637PA536PA435VDCIA34ANT33VINTA32X32MI31X32MO30PB1829PB1928PB2027PB2126PB22Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.838.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
12345678910252627282930313233342423222120191817161514131211484746454443424140393837363549E=5.00mm · Pitch e=0.35mmD=5.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.35mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDCIDI/OMultiplexed I/O & Peripheral Pin VDCID (General)
2VSWI/OMultiplexed I/O & Peripheral Pin VSW (General)
3VDD33/VIO33PowerPower Supply Input (VDD33/VIO33 — 3.3V / 5.0V Standard Logic)
4PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
5PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
6PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
7PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
8PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
9PB17I/OMultiplexed I/O & Peripheral Pin PB17 (General)
10PB16I/OMultiplexed I/O & Peripheral Pin PB16 (General)
11PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
12PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
13PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
14PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
15PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
16PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
17PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
18PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
19PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
20PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
21PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
22PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
23PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
24PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
25PB23I/OMultiplexed I/O & Peripheral Pin PB23 (General)
26PB22I/OMultiplexed I/O & Peripheral Pin PB22 (General)
27PB21I/OMultiplexed I/O & Peripheral Pin PB21 (General)
28PB20I/OMultiplexed I/O & Peripheral Pin PB20 (General)
29PB19I/OMultiplexed I/O & Peripheral Pin PB19 (General)
30PB18I/OMultiplexed I/O & Peripheral Pin PB18 (General)
31X32MOI/OMultiplexed I/O & Peripheral Pin X32MO (General)
32X32MII/OMultiplexed I/O & Peripheral Pin X32MI (General)
33VINTAPowerPower Supply Input (VINTA — 3.3V / 5.0V Standard Logic)
34ANTI/OMultiplexed I/O & Peripheral Pin ANT (General)
35VDCIAI/OMultiplexed I/O & Peripheral Pin VDCIA (General)
36PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
37PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
38PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
39PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
40PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
41PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
42PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
43PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
44PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
45PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
46PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
47PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
48PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
49EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 VDCID
I/O
Multiplexed I/O & Peripheral Pin VDCID (General)
Design note: Signal terminal VDCID (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VDCID. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH582M-EVT (WCH · QFN-48_L5.0-W5.0-P0.35-BL-EP)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP) - 4. Package Dimensions (D×E×A)
QFN-48_L5.0-W5.0-P0.35-BL-EP · 5.00×5.00mm · Pitch 0.35mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CH582 / CH583
P1 · p01_fig01288×164px
CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP) — CH583 是集成BLE 无线通讯的32 位RISC 微控制器。片上集成2Mbps 低功耗蓝牙BLE 通讯模块、 2 个全速USB 主机和设备控制器及收发器、2 个SPI、4 个串口、ADC、触摸按键检测模块、RTC 等丰 富的外设资源。 功能
CH583 是集成BLE 无线通讯的32 位RISC 微控制器。片上集成2Mbps 低功耗蓝牙BLE 通讯模块、 2 个全速USB 主机和设备控制器及收发器、2 个SPI、4 个串口、ADC、触摸按键检测模块、RTC 等丰 富的外设资源。 功能
P3 · p03_fig011757×1981px
CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP) — 第1 章 引脚信息
第1 章 引脚信息
P3 · p03_fig01P3
CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P66 · p66_fig011713×2764px
CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP) — 64 | 位RB_SPI_IF_BYTE_END 的功能： 1：使能；0：禁止。 3 Reserved R0 保留。 0 | 2 RB_SPI_DMA_LOOP RW | DMA 地址循环功能使能位（仅SPI0 支 持）： 1：使能地址循环；0：禁止地址循环。 如果使能DMA 地址循环，当DMA 地址增 加到设置的末尾地址时，自动循环指向 设置的首地址。 | 0 | 1 Reserved R0 保留。 0 | 0 RB_SPI_DMA_ENABLE RW DMA 功能使能位（
64 | 位RB_SPI_IF_BYTE_END 的功能： 1：使能；0：禁止。 3 Reserved R0 保留。 0 | 2 RB_SPI_DMA_LOOP RW | DMA 地址循环功能使能位（仅SPI0 支 持）： 1：使能地址循环；0：禁止地址循环。 如果使能DMA 地址循环，当DMA 地址增 加到设置的末尾地址时，自动循环指向 设置的首地址。 | 0 | 1 Reserved R0 保留。 0 | 0 RB_SPI_DMA_ENABLE RW DMA 功能使能位（
P67 · p67_fig011713×2520px
CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP) — 位 名称 访问 描述 复位值 [7：0] R8_SPIx_FIFO_COUNT1 RW 当前FIFO 中字节计数。 00h
位 名称 访问 描述 复位值 [7：0] R8_SPIx_FIFO_COUNT1 RW 当前FIFO 中字节计数。 00h
P68 · p68_fig011713×847px
CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP) — 66 | 同R8_SPIx_FIFO_COUNT。 SPI 收发数据总长度寄存器(R16_SPIx_TOTAL_CNT) (x=0/1) | 位 名称 访问 描述 复位值 | [15：0] R16_SPIx_TOTAL_CNT RW | 主机模式下SPI 数据收发总字节数，低 12 位有效。在使用DMA 时一次最多可以 收发4095 个字节。不支持从机模式。 | 0000h | SPI 数据FIFO 寄存器(R8_SPIx_FIFO) (x=0/1) | 位 名称 访问 描述
66 | 同R8_SPIx_FIFO_COUNT。 SPI 收发数据总长度寄存器(R16_SPIx_TOTAL_CNT) (x=0/1) | 位 名称 访问 描述 复位值 | [15：0] R16_SPIx_TOTAL_CNT RW | 主机模式下SPI 数据收发总字节数，低 12 位有效。在使用DMA 时一次最多可以 收发4095 个字节。不支持从机模式。 | 0000h | SPI 数据FIFO 寄存器(R8_SPIx_FIFO) (x=0/1) | 位 名称 访问 描述
P68 · p68_fig021713×988px
CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP) — SPI 支持模式0 和模式3 两种传输格式，通过设置R8_SPIx_CTRL_MOD 的RB_SPI_MST_SCK_MOD 进 行选择。总是在SCK 上升沿采样串行数据输入，在下降沿输出串行数据。
SPI 支持模式0 和模式3 两种传输格式，通过设置R8_SPIx_CTRL_MOD 的RB_SPI_MST_SCK_MOD 进 行选择。总是在SCK 上升沿采样串行数据输入，在下降沿输出串行数据。
P110 · p110_fig011345×1019px
CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP) — 封装形式 塑体宽度 引脚间距 封装说明 订货型号
封装形式 塑体宽度 引脚间距 封装说明 订货型号
P110 · p110_fig01P110
CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP) — Datasheet Page 110 (p110_fig01)
Datasheet Page 110 (p110_fig01)

Technical Specifications & Part Details (CH582M-EVT)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP) is a 48-pin standard electronic & interconnect component featuring a 5.00 × 5.00 × 0.85 mm mechanical envelope (lead pitch e = 0.35 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, SPI, I2C, ADC interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-48_L5.0-W5.0-P0.35-BL-EP)
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.35 mm (13.8 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, SPI, I2C, ADC
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.35mm
OK
IPC-7525 60% Solder PasteEPAD 3.70×3.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-48_L5.0-W5.0-P0.35-BL-EP)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.35mm
Pad Size (W × L)Level B
0.16 × 0.75 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-48_L5.0-W5.0-P0.35-BL-EP
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP)?

Manufactured by WCH, the CH582M-EVT is housed in a QFN-48_L5.0-W5.0-P0.35-BL-EP package with 49 pins and a 0.35 mm lead pitch. Key pins include: 1 (VDCID: Multiplexed I/O & Peripheral Pin VDCID (General)), 2 (VSW: Multiplexed I/O & Peripheral Pin VSW (General)), 3 (VDD33/VIO33: Power Supply Input (VDD33/VIO33 — 3.3V / 5.0V Standard Logic)), 4 (PA7: Multiplexed I/O & Peripheral Pin PA7 (General)), 5 (PA8: Multiplexed I/O & Peripheral Pin PA8 (General)), 6 (PA9: Multiplexed I/O & Peripheral Pin PA9 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH582M-EVT?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH582M-EVT (QFN-48_L5.0-W5.0-P0.35-BL-EP) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.35 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 3.70 × 3.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH582M-EVT?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH582M-EVT (WCH, QFN-48_L5.0-W5.0-P0.35-BL-EP) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & CH582 / CH583 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDCIDDigital_IOSignal terminal VDCID (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VDCID. Supported peripheral buses: General.
2VSWDigital_IOSignal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: General.
3VDD33/VIO33Power_InPrimary positive power supply input (VDD33/VIO33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
5PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
6PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
7PB9Digital_IOSignal terminal PB9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
8PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
9PB17Digital_IOSignal terminal PB17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB17. Supported peripheral buses: General.
10PB16Digital_IOSignal terminal PB16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB16. Supported peripheral buses: General.
11PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
12PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
13PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
14PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
15PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
16PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
17PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
18PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
19PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
20PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
21PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
22PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
23PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
24PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
25PB23Digital_IOSignal terminal PB23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB23. Supported peripheral buses: General.
26PB22Digital_IOSignal terminal PB22 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB22. Supported peripheral buses: General.
27PB21Digital_IOSignal terminal PB21 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB21. Supported peripheral buses: General.
28PB20Digital_IOSignal terminal PB20 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB20. Supported peripheral buses: General.
29PB19Digital_IOSignal terminal PB19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB19. Supported peripheral buses: General.
30PB18Digital_IOSignal terminal PB18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB18. Supported peripheral buses: General.
31X32MODigital_IOSignal terminal X32MO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MO. Supported peripheral buses: General.
32X32MIDigital_IOSignal terminal X32MI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MI. Supported peripheral buses: General.
33VINTAPower_InPrimary positive power supply input (VINTA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
34ANTRF_50OhmSignal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General.
35VDCIADigital_IOSignal terminal VDCIA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VDCIA. Supported peripheral buses: General.
36PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
37PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
38PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
39PA0Digital_IOSignal terminal PA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
40PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
41PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
42PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
43PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
44PA14Digital_IOSignal terminal PA14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
45PA13Digital_IOSignal terminal PA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
46PA12Digital_IOSignal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
47PA11Digital_IOSignal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
48PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
49EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
ExplorePartsPackagesMFRsUpload