ChipDocs.org
⌘K
2284 PARTSUpload PDF
C2922573 (QFN-28_L4.0-W4.0-P0.40-BL-EP2.8) — Symbol, Footprint IPC-7351B & 3D STEP Model

C2922573

SemiconductorQFN-28_L4.0-W4.0-P0.40-BL-EP2.8 · 29 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C2922573 (QFN-28_L4.0-W4.0-P0.40-BL-EP2.8)1LNA_IN2VDD3P33VDD3P34XTAL_32K_P5XTAL_32K_N6GPIO27CHIP_EN8GPIO39MTMS10MTDI11VDD3P3_RTC12MTCK13MTDO14GPIO815GPIO929GND28VDDA27VDDA26XTAL_P25XTAL_N24U0TXD23U0RXD22GPIO1921GPIO1820NC19NC18TEST/SCL17VDD3P3_CPU16GPIO10Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.225.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
4567321891011121314151617181920212223242526272829E=4.00mm · Pitch e=0.40mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1LNA_INI/OMultiplexed I/O & Peripheral Pin LNA_IN (General)
2VDD3P3PowerPower Supply Input (VDD3P3 — 3.3V / 5.0V Standard Logic)
3VDD3P3PowerPower Supply Input (VDD3P3 — 3.3V / 5.0V Standard Logic)
4XTAL_32K_PI/OMultiplexed I/O & Peripheral Pin XTAL_32K_P (RTC/CLK)
5XTAL_32K_NI/OMultiplexed I/O & Peripheral Pin XTAL_32K_N (RTC/CLK)
6GPIO2I/OMultiplexed I/O & Peripheral Pin GPIO2 (General)
7CHIP_ENI/OMultiplexed I/O & Peripheral Pin CHIP_EN (General)
8GPIO3I/OMultiplexed I/O & Peripheral Pin GPIO3 (General)
9MTMSI/OMultiplexed I/O & Peripheral Pin MTMS (SWD/JTAG)
10MTDII/OMultiplexed I/O & Peripheral Pin MTDI (SWD/JTAG)
11VDD3P3_RTCPowerPower Supply Input (VDD3P3_RTC — 3.3V / 5.0V Standard Logic)
12MTCKI/OMultiplexed I/O & Peripheral Pin MTCK (SWD/JTAG)
13MTDOI/OMultiplexed I/O & Peripheral Pin MTDO (SWD/JTAG)
14GPIO8I/OMultiplexed I/O & Peripheral Pin GPIO8 (General)
15GPIO9I/OMultiplexed I/O & Peripheral Pin GPIO9 (General)
16GPIO10I/OMultiplexed I/O & Peripheral Pin GPIO10 (General)
17VDD3P3_CPUPowerPower Supply Input (VDD3P3_CPU — 3.3V / 5.0V Standard Logic)
18TEST/SCLI/OMultiplexed I/O & Peripheral Pin TEST/SCL (I2C)
19NCI/OMultiplexed I/O & Peripheral Pin NC (General)
20NCI/OMultiplexed I/O & Peripheral Pin NC (General)
21GPIO18I/OMultiplexed I/O & Peripheral Pin GPIO18 (General)
22GPIO19I/OMultiplexed I/O & Peripheral Pin GPIO19 (General)
23U0RXDI/OMultiplexed I/O & Peripheral Pin U0RXD (UART)
24U0TXDI/OMultiplexed I/O & Peripheral Pin U0TXD (UART)
25XTAL_NI/OMultiplexed I/O & Peripheral Pin XTAL_N (RTC/CLK)
26XTAL_PI/OMultiplexed I/O & Peripheral Pin XTAL_P (RTC/CLK)
27VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
28VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
29GNDGNDGround Reference Pin (GND)
PIN 1 LNA_IN
I/O
Multiplexed I/O & Peripheral Pin LNA_IN (General)
Design note: Signal terminal LNA_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LNA_IN. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C2922573 (Semiconductor · QFN-28_L4.0-W4.0-P0.40-BL-EP2.8)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C2922573 (QFN-28_L4.0-W4.0-P0.40-BL-EP2.8) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C2922573 (QFN-28_L4.0-W4.0-P0.40-BL-EP2.8) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C2922573 (QFN-28_L4.0-W4.0-P0.40-BL-EP2.8) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C2922573 (QFN-28_L4.0-W4.0-P0.40-BL-EP2.8) - 4. Package Dimensions (D×E×A)
QFN-28_L4.0-W4.0-P0.40-BL-EP2.8 · 4.00×4.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
C2922573 (QFN-28_L4.0-W4.0-P0.40-BL-EP2.8) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
C2922573 (QFN-28_L4.0-W4.0-P0.40-BL-EP2.8) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C2922573)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:C2922573 (QFN-28_L4.0-W4.0-P0.40-BL-EP2.8) is a 28-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated I2C, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-28_L4.0-W4.0-P0.40-BL-EP2.8)
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 2.80×2.80mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-28_L4.0-W4.0-P0.40-BL-EP2.8)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.70 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-28_L4.0-W4.0-P0.40-BL-EP2.8
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C2922573 (QFN-28_L4.0-W4.0-P0.40-BL-EP2.8)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C2922573 (QFN-28_L4.0-W4.0-P0.40-BL-EP2.8)?

Manufactured by Semiconductor, the C2922573 is housed in a QFN-28_L4.0-W4.0-P0.40-BL-EP2.8 package with 29 pins and a 0.40 mm lead pitch. Key pins include: 1 (LNA_IN: Multiplexed I/O & Peripheral Pin LNA_IN (General)), 2 (VDD3P3: Power Supply Input (VDD3P3 — 3.3V / 5.0V Standard Logic)), 3 (VDD3P3: Power Supply Input (VDD3P3 — 3.3V / 5.0V Standard Logic)), 4 (XTAL_32K_P: Multiplexed I/O & Peripheral Pin XTAL_32K_P (RTC/CLK)), 5 (XTAL_32K_N: Multiplexed I/O & Peripheral Pin XTAL_32K_N (RTC/CLK)), 6 (GPIO2: Multiplexed I/O & Peripheral Pin GPIO2 (General)).

What are the IPC-7351B PCB Footprint dimensions for C2922573?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C2922573 (QFN-28_L4.0-W4.0-P0.40-BL-EP2.8) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.40 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 2.80 × 2.80 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C2922573?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C2922573 (Semiconductor, QFN-28_L4.0-W4.0-P0.40-BL-EP2.8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & ESP8685 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1LNA_INDigital_IOSignal terminal LNA_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LNA_IN. Supported peripheral buses: General.
2VDD3P3Power_InPrimary positive power supply input (VDD3P3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3VDD3P3Power_InPrimary positive power supply input (VDD3P3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4XTAL_32K_PDigital_IOSignal terminal XTAL_32K_P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XTAL_32K_P. Supported peripheral buses: RTC/CLK.
5XTAL_32K_NDigital_IOSignal terminal XTAL_32K_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XTAL_32K_N. Supported peripheral buses: RTC/CLK.
6GPIO2Digital_IOSignal terminal GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO2. Supported peripheral buses: General.
7CHIP_ENDigital_IOSignal terminal CHIP_EN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CHIP_EN. Supported peripheral buses: General.
8GPIO3Digital_IOSignal terminal GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO3. Supported peripheral buses: General.
9MTMSDigital_IOSignal terminal MTMS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MTMS. Supported peripheral buses: SWD/JTAG.
10MTDIDigital_IOSignal terminal MTDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MTDI. Supported peripheral buses: SWD/JTAG.
11VDD3P3_RTCPower_InPrimary positive power supply input (VDD3P3_RTC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
12MTCKDigital_IOSignal terminal MTCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MTCK. Supported peripheral buses: SWD/JTAG.
13MTDODigital_IOSignal terminal MTDO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MTDO. Supported peripheral buses: SWD/JTAG.
14GPIO8Digital_IOSignal terminal GPIO8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO8. Supported peripheral buses: General.
15GPIO9Digital_IOSignal terminal GPIO9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO9. Supported peripheral buses: General.
16GPIO10Digital_IOSignal terminal GPIO10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO10. Supported peripheral buses: General.
17VDD3P3_CPUPower_InPrimary positive power supply input (VDD3P3_CPU) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
18TEST/SCLDigital_IOSignal terminal TEST/SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TEST/SCL. Supported peripheral buses: I2C.
19NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
20NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
21GPIO18Digital_IOSignal terminal GPIO18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO18. Supported peripheral buses: General.
22GPIO19Digital_IOSignal terminal GPIO19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO19. Supported peripheral buses: General.
23U0RXDDigital_IOSignal terminal U0RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: U0RXD. Supported peripheral buses: UART.
24U0TXDDigital_IOSignal terminal U0TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: U0TXD. Supported peripheral buses: UART.
25XTAL_NDigital_IOSignal terminal XTAL_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XTAL_N. Supported peripheral buses: RTC/CLK.
26XTAL_PDigital_IOSignal terminal XTAL_P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XTAL_P. Supported peripheral buses: RTC/CLK.
27VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
28VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
29GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
ExplorePartsPackagesMFRsUpload