Mechanical Dimensions & Land Pattern (QFN-20(2.5x4.5))
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-20(2.5x4.5) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH482X (QFN-20(2.5x4.5))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH482X (QFN-20(2.5x4.5))?
Manufactured by WCH, the CH482X is housed in a QFN-20(2.5x4.5) package with 21 pins and a 0.50 mm lead pitch. Key pins include: 1 (EN#: Multiplexed I/O & Peripheral Pin EN# (General)), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (GND: Ground Reference Pin (GND)), 5 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), 6 (IO3: GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)).
What are the IPC-7351B PCB Footprint dimensions for CH482X?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH482X (QFN-20(2.5x4.5)) has a nominal body envelope of 2.50 × 4.50 mm, pitch e = 0.50 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 3.00 × 1.00 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH482X?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH482X (WCH, QFN-20(2.5x4.5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (21 pins) & CH481 / CH482 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | EN# | Digital_IO | Signal terminal EN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: EN#. Supported peripheral buses: General. |
| 2 | IO2 | Digital_IO | General Purpose Digital I/O Pin IO2 |
| 3 | 3V3 | Power_In | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 5 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 6 | IO3 | Digital_IO | GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap) |
| 7 | NC | No_Connect | No Connect (Leave Floating) |
| 8 | SEL | Digital_IO | Signal terminal SEL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEL. Supported peripheral buses: General. |
| 9 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 10 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 11 | IO6 | Digital_IO | GPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5 |
| 12 | IO7 | Digital_IO | GPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6 |
| 13 | IO15 | Digital_IO | GPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P |
| 14 | IO16 | Digital_IO | GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N |
| 15 | IO17 | Digital_IO | GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6 |
| 16 | IO18 | Digital_IO | GPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3 |
| 17 | IO8 | Digital_IO | GPIO8 / RTC_GPIO8 / TOUCH8 / ADC1_CH7 / SUBSPICS1 |
| 18 | IO19 | Digital_IO | GPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8 |
| 19 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 20 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 21 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |