ChipDocs.org
⌘K
2284 PARTSUpload PDF
CH448F (QFN-24-EP(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH448F

WCHID: C2912958QFN-24-EP(4x4) · 25 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH448F (QFN-24-EP(4x4))1SEL2 、 SEL1 2VDD3A0X A0Y 、4A0X A0Y 、5A1X A1Y 、6A1X A1Y 、7A2X A2Y 、8A2X A2Y 、9A3X A3Y 、10A3X A3Y 、11XEN#12YEN#13AY25GND24SEL2 、 SEL1 23SEL2 、 SEL1 22A4X A4Y 、21A4X A4Y 、20A5X A5Y 、19A5X A5Y 、18A6X A6Y 、17A6X A6Y 、16A7X A7Y 、15A7X A7Y 、14AXGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.222.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425E=4.00mm · Pitch e=0.50mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (25/25)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1SEL2 、 SEL1 、 SEL0I/OMultiplexed I/O & Peripheral Pin SEL2 、 SEL1 、 SEL0 (General)
2VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
3A0X A0Y 、I/OMultiplexed I/O & Peripheral Pin A0X A0Y 、 (General)
4A0X A0Y 、I/OMultiplexed I/O & Peripheral Pin A0X A0Y 、 (General)
5A1X A1Y 、I/OMultiplexed I/O & Peripheral Pin A1X A1Y 、 (General)
6A1X A1Y 、I/OMultiplexed I/O & Peripheral Pin A1X A1Y 、 (General)
7A2X A2Y 、I/OMultiplexed I/O & Peripheral Pin A2X A2Y 、 (General)
8A2X A2Y 、I/OMultiplexed I/O & Peripheral Pin A2X A2Y 、 (General)
9A3X A3Y 、I/OMultiplexed I/O & Peripheral Pin A3X A3Y 、 (General)
10A3X A3Y 、I/OMultiplexed I/O & Peripheral Pin A3X A3Y 、 (General)
11XEN#I/OMultiplexed I/O & Peripheral Pin XEN# (General)
12YEN#I/OMultiplexed I/O & Peripheral Pin YEN# (General)
13AYI/OMultiplexed I/O & Peripheral Pin AY (General)
14AXI/OMultiplexed I/O & Peripheral Pin AX (General)
15A7X A7Y 、I/OMultiplexed I/O & Peripheral Pin A7X A7Y 、 (General)
16A7X A7Y 、I/OMultiplexed I/O & Peripheral Pin A7X A7Y 、 (General)
17A6X A6Y 、I/OMultiplexed I/O & Peripheral Pin A6X A6Y 、 (General)
18A6X A6Y 、I/OMultiplexed I/O & Peripheral Pin A6X A6Y 、 (General)
19A5X A5Y 、I/OMultiplexed I/O & Peripheral Pin A5X A5Y 、 (General)
20A5X A5Y 、I/OMultiplexed I/O & Peripheral Pin A5X A5Y 、 (General)
21A4X A4Y 、I/OMultiplexed I/O & Peripheral Pin A4X A4Y 、 (General)
22A4X A4Y 、I/OMultiplexed I/O & Peripheral Pin A4X A4Y 、 (General)
23SEL2 、 SEL1 、 SEL0I/OMultiplexed I/O & Peripheral Pin SEL2 、 SEL1 、 SEL0 (General)
24SEL2 、 SEL1 、 SEL0I/OMultiplexed I/O & Peripheral Pin SEL2 、 SEL1 、 SEL0 (General)
25GNDGNDGround Reference Pin (GND)
PIN 1 SEL2 、 SEL1 、 SEL0
I/O
Multiplexed I/O & Peripheral Pin SEL2 、 SEL1 、 SEL0 (General)
Design note: 八选 模拟开关的选择输入 一 ： 000 选择0#端（A0*） ；001 选择1#端（A1*） ； 010 选择2#端（A2*） ；011 选择3#端（A3*） ； 100 选择4#端（A4*） ；101 选择5#端（A5*） ； 110 选择6#端（A6*） ；111 选择7#端（A7*）
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH448F (WCH · QFN-24-EP(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH448F (QFN-24-EP(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH448F (QFN-24-EP(4x4)) - 2. Standard Pinout (Top View)
True package pinout (25 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH448F (QFN-24-EP(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH448F (QFN-24-EP(4x4)) - 4. Package Dimensions (D×E×A)
QFN-24-EP(4x4) · 4.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH448F (QFN-24-EP(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (25 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH448F (QFN-24-EP(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for CH445 / CH448 / CH440
P15 · p15_fig01EXACT PACKAGE
CH448F (QFN-24-EP(4x4)) — 8.5. QFN24-4X4
8.5. QFN24-4X4
P2 · p02_fig011491×1615px
CH448F (QFN-24-EP(4x4)) — 3、引脚排列
3、引脚排列
P2 · p02_fig01P2
CH448F (QFN-24-EP(4x4)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P3 · p03_fig011729×2206px
CH448F (QFN-24-EP(4x4)) — 2、QFN 或DFN 封装的底板标示为0#引脚，对于CH448F 是必要连接。 3、CH442Q 与CH9442Q 引脚兼容，CH9442Q 支持Type-C 充电口USB 信号，耐压28V。 4、原型号CH440E 已用新型号CH442E 代替，引脚和功能相同。 5、CH340K 为盘装，每盘整包装数量为3000 只。 6、CH442Q、CH340K、CH443L 封装体积较小，正面印字仅有代号42、43、43 而不含全部型号。 | 4、引脚定义 | 4.1. CH340G
2、QFN 或DFN 封装的底板标示为0#引脚，对于CH448F 是必要连接。 3、CH442Q 与CH9442Q 引脚兼容，CH9442Q 支持Type-C 充电口USB 信号，耐压28V。 4、原型号CH440E 已用新型号CH442E 代替，引脚和功能相同。 5、CH340K 为盘装，每盘整包装数量为3000 只。 6、CH442Q、CH340K、CH443L 封装体积较小，正面印字仅有代号42、43、43 而不含全部型号。 | 4、引脚定义 | 4.1. CH340G
P9 · p09_fig011725×2761px
CH448F (QFN-24-EP(4x4)) — CH440/CH442/CH443/CH444/CH445/CH448 手册 ９ | 6.3. 额定5V 芯片电气参数@3.3V（测试条件：TA=25℃，VCC=VDD=3.3V，不含CH445） | 6.4. 额定5V 芯片模拟开关时序参数（测试条件：TA=25℃，VCC=VDD=5V，VANA=0V，不含CH445） | 名称 参数说明 最小值 典型值 最大值 单位 CIN 数字输入引脚电容，F=1MHz 4 8 pF | COFF CH448 开关关闭时模拟信号引脚电容
CH440/CH442/CH443/CH444/CH445/CH448 手册 ９ | 6.3. 额定5V 芯片电气参数@3.3V（测试条件：TA=25℃，VCC=VDD=3.3V，不含CH445） | 6.4. 额定5V 芯片模拟开关时序参数（测试条件：TA=25℃，VCC=VDD=5V，VANA=0V，不含CH445） | 名称 参数说明 最小值 典型值 最大值 单位 CIN 数字输入引脚电容，F=1MHz 4 8 pF | COFF CH448 开关关闭时模拟信号引脚电容
P9 · p09_fig01P9
CH448F (QFN-24-EP(4x4)) — Datasheet Page 9 (p09_fig01)
Datasheet Page 9 (p09_fig01)
P11 · p11_fig011506×749px
CH448F (QFN-24-EP(4x4)) — VCOM(V) 6.8.2 CH445 的模拟开关导通电阻RON 与模拟信号电压VCOM 的相关性（TA=25℃） RON (Ω)
VCOM(V) 6.8.2 CH445 的模拟开关导通电阻RON 与模拟信号电压VCOM 的相关性（TA=25℃） RON (Ω)
P11 · p11_fig021543×684px
CH448F (QFN-24-EP(4x4)) — VCOM(V)
VCOM(V)
P15 · p15_fig021323×1185px
CH448F (QFN-24-EP(4x4)) — 8.6. TSSOP16
8.6. TSSOP16
P17 · p17_fig011210×1387px
CH448F (QFN-24-EP(4x4)) — D 6 =a] 7 1 a a TEE.
D 6 =a] 7 1 a a TEE.

Technical Specifications & Part Details (CH448F)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH448F (QFN-24-EP(4x4)) is a 24-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 1.00 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
550 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 1.00 mm (A1=0.03 mm)
Package family: QFN (QFN-24-EP(4x4))
Pin Count & Lead PitchN / e
24 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol25 auto-grouped pins
OK
IPC-7351B Land Pattern25 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 2.80×2.80mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-24-EP(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.50mm
Pad Size (W × L)Level B
0.29 × 0.77 mm
Pins / Total PadsTopology
25P / 25Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-24-EP(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH448F (QFN-24-EP(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH448F (QFN-24-EP(4x4))?

Manufactured by WCH, the CH448F is housed in a QFN-24-EP(4x4) package with 25 pins and a 0.50 mm lead pitch. Key pins include: 1 (SEL2 、 SEL1 、 SEL0: Multiplexed I/O & Peripheral Pin SEL2 、 SEL1 、 SEL0 (General)), 2 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), 3 (A0X A0Y 、: Multiplexed I/O & Peripheral Pin A0X A0Y 、 (General)), 4 (A0X A0Y 、: Multiplexed I/O & Peripheral Pin A0X A0Y 、 (General)), 5 (A1X A1Y 、: Multiplexed I/O & Peripheral Pin A1X A1Y 、 (General)), 6 (A1X A1Y 、: Multiplexed I/O & Peripheral Pin A1X A1Y 、 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH448F?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH448F (QFN-24-EP(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 25 copper pads plus a central exposed thermal pad (EPAD) of 2.80 × 2.80 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH448F?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH448F (WCH, QFN-24-EP(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (25 pins) & CH445 / CH448 / CH440 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1SEL2 、 SEL1 、 SEL0Digital_IOSignal terminal SEL2 、 SEL1 、 SEL0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEL2 、 SEL1 、 SEL0. Supported peripheral buses: General.
2VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3A0X A0Y 、Digital_IOSignal terminal A0X A0Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0X A0Y 、. Supported peripheral buses: General.
4A0X A0Y 、Digital_IOSignal terminal A0X A0Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0X A0Y 、. Supported peripheral buses: General.
5A1X A1Y 、Digital_IOSignal terminal A1X A1Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1X A1Y 、. Supported peripheral buses: General.
6A1X A1Y 、Digital_IOSignal terminal A1X A1Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1X A1Y 、. Supported peripheral buses: General.
7A2X A2Y 、Digital_IOSignal terminal A2X A2Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A2X A2Y 、. Supported peripheral buses: General.
8A2X A2Y 、Digital_IOSignal terminal A2X A2Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A2X A2Y 、. Supported peripheral buses: General.
9A3X A3Y 、Digital_IOSignal terminal A3X A3Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A3X A3Y 、. Supported peripheral buses: General.
10A3X A3Y 、Digital_IOSignal terminal A3X A3Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A3X A3Y 、. Supported peripheral buses: General.
11XEN#Digital_IOSignal terminal XEN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XEN#. Supported peripheral buses: General.
12YEN#Digital_IOSignal terminal YEN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: YEN#. Supported peripheral buses: General.
13AYDigital_IOSignal terminal AY (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AY. Supported peripheral buses: General.
14AXDigital_IOSignal terminal AX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AX. Supported peripheral buses: General.
15A7X A7Y 、Digital_IOSignal terminal A7X A7Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A7X A7Y 、. Supported peripheral buses: General.
16A7X A7Y 、Digital_IOSignal terminal A7X A7Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A7X A7Y 、. Supported peripheral buses: General.
17A6X A6Y 、Digital_IOSignal terminal A6X A6Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A6X A6Y 、. Supported peripheral buses: General.
18A6X A6Y 、Digital_IOSignal terminal A6X A6Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A6X A6Y 、. Supported peripheral buses: General.
19A5X A5Y 、Digital_IOSignal terminal A5X A5Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A5X A5Y 、. Supported peripheral buses: General.
20A5X A5Y 、Digital_IOSignal terminal A5X A5Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A5X A5Y 、. Supported peripheral buses: General.
21A4X A4Y 、Digital_IOSignal terminal A4X A4Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A4X A4Y 、. Supported peripheral buses: General.
22A4X A4Y 、Digital_IOSignal terminal A4X A4Y 、 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A4X A4Y 、. Supported peripheral buses: General.
23SEL2 、 SEL1 、 SEL0Digital_IOSignal terminal SEL2 、 SEL1 、 SEL0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEL2 、 SEL1 、 SEL0. Supported peripheral buses: General.
24SEL2 、 SEL1 、 SEL0Digital_IOSignal terminal SEL2 、 SEL1 、 SEL0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEL2 、 SEL1 、 SEL0. Supported peripheral buses: General.
25GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
ExplorePartsPackagesMFRsUpload