LQFP-48(7x7) · 48P
Synchronized Pinout (Symbol / 2D / 3D) (100/100)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| A1 | PB9 | I/O | Multiplexed I/O & Peripheral Pin PB9 (UART, SPI, I2C) |
| A2 | PB8 | I/O | Multiplexed I/O & Peripheral Pin PB8 (SPI, I2C) |
| A3 | BOOT0 | I | Input-Only Pin BOOT0 (General) |
| A4 | PB5 | I/O | Multiplexed I/O & Peripheral Pin PB5 (UART, SPI, I2C, PWM) |
| A5 | PB3(JTDO/ TRACESWO) | I/O | Multiplexed I/O & Peripheral Pin PB3(JTDO/ TRACESWO) (SPI, I2C, SWD/JTAG) |
| A6 | PD6 | I/O | Multiplexed I/O & Peripheral Pin PD6 (SPI, I2C) |
| A7 | PD4 | I/O | Multiplexed I/O & Peripheral Pin PD4 (UART) |
| A8 | PD3 | I/O | Multiplexed I/O & Peripheral Pin PD3 (UART, SPI) |
| A9 | PD1 | I/O | Multiplexed I/O & Peripheral Pin PD1 (UART) |
| A10 | PC11 | I/O | Multiplexed I/O & Peripheral Pin PC11 (UART, SPI, I2C) |
| A11 | PA15 (JTDI) | I/O | Multiplexed I/O & Peripheral Pin PA15 (JTDI) (UART, SPI, SWD/JTAG) |
| A12 | PC10 | I/O | Multiplexed I/O & Peripheral Pin PC10 (UART, SPI, I2C) |
| B1 | PE0 | I/O | Multiplexed I/O & Peripheral Pin PE0 (SPI) |
| B2 | PE4 | I/O | Multiplexed I/O & Peripheral Pin PE4 (SPI) |
| B3 | PE3 | I/O | Multiplexed I/O & Peripheral Pin PE3 (General) |
| B4 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (UART, I2C) |
| B5 | PB4 (NJTRST) | I/O | Multiplexed I/O & Peripheral Pin PB4 (NJTRST) (SPI, I2C, SWD/JTAG) |
| B6 | PD7 | I/O | Multiplexed I/O & Peripheral Pin PD7 (SPI, I2C) |
| B7 | PD5 | I/O | Multiplexed I/O & Peripheral Pin PD5 (SPI) |
| B8 | PD2 | I/O | Multiplexed I/O & Peripheral Pin PD2 (UART) |
| B9 | PD0 | I/O | Multiplexed I/O & Peripheral Pin PD0 (UART) |
| B10 | PC12 | I/O | Multiplexed I/O & Peripheral Pin PC12 (UART, SPI) |
| B11 | PA14(JTCK/ SWCLK) | I/O | Multiplexed I/O & Peripheral Pin PA14(JTCK/ SWCLK) (SWD/JTAG) |
| B12 | PA13(JTMS/SW DIO) | I/O | Multiplexed I/O & Peripheral Pin PA13(JTMS/SW DIO) (SWD/JTAG) |
| C1 | PE2 | I/O | Multiplexed I/O & Peripheral Pin PE2 (SPI) |
| C2 | PE5 | I/O | Multiplexed I/O & Peripheral Pin PE5 (SPI) |
| C3 | VSS | GND | Ground Reference Pin (VSS) |
| C4 | VCAP | I/O | Multiplexed I/O & Peripheral Pin VCAP (General) |
| C5 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (UART, SPI, I2C) |
| C8 | VDDIO2 | Power | Power Supply Input (VDDIO2 — 3.3V VDD (Max 4.0V)) |
| C9 | VSS | GND | Ground Reference Pin (VSS) |
| C10 | VDDUSB | Power | Power Supply Input (VDDUSB — 3.3V VDD (Max 4.0V)) |
| C11 | PA12 | I/O | Multiplexed I/O & Peripheral Pin PA12 (USB, UART, SPI) |
| C12 | PA11 | I/O | Multiplexed I/O & Peripheral Pin PA11 (USB, UART, SPI, PWM) |
| D1 | VBAT | Power | Power Supply Input (VBAT — 3.3V VDD (Max 4.0V)) |
| D2 | PE6 | I/O | Multiplexed I/O & Peripheral Pin PE6 (SPI) |
| D3 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| D10 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| D11 | PA10 | I/O | Multiplexed I/O & Peripheral Pin PA10 (General) |
| D12 | PA9 | I/O | Multiplexed I/O & Peripheral Pin PA9 (SPI) |
| E1 | IOE1 | I/O | General Purpose Digital I/O Pin IOE1 |
| E2 | PC15 - OSC32_OUT | I/O | Multiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK) |
| E3 | PC13 | I/O | Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK) |
| E10 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (UART, SPI, I2C, RTC/CLK) |
| E11 | PC9 | I/O | Multiplexed I/O & Peripheral Pin PC9 (I2C, RTC/CLK) |
| E12 | PC8 | I/O | Multiplexed I/O & Peripheral Pin PC8 (UART) |
| F1 | PH0OSC IN -_ (PH0) | I/O | Multiplexed I/O & Peripheral Pin PH0OSC IN -_ (PH0) (RTC/CLK) |
| F2 | PH1OSC OUT -_ (PH1) | I/O | Multiplexed I/O & Peripheral Pin PH1OSC OUT -_ (PH1) (RTC/CLK) |
| F11 | PC7 | I/O | Multiplexed I/O & Peripheral Pin PC7 (I2C) |
| F12 | PC6 | I/O | Multiplexed I/O & Peripheral Pin PC6 (UART, PWM) |
| G1 | PC0 | I/O | Multiplexed I/O & Peripheral Pin PC0 (SPI, ADC) |
| G2 | NRST | I | System Enable & Hardware Reset (NRST) |
| G11 | PD14 | I/O | Multiplexed I/O & Peripheral Pin PD14 (General) |
| G12 | PD15 | I/O | Multiplexed I/O & Peripheral Pin PD15 (General) |
| H1 | PC2 | I/O | Multiplexed I/O & Peripheral Pin PC2 (SPI, ADC) |
| H2 | PC3 | I/O | Multiplexed I/O & Peripheral Pin PC3 (SPI, ADC) |
| H3 | PC1 | I/O | Multiplexed I/O & Peripheral Pin PC1 (SPI, ADC) |
| H10 | PD11 | I/O | Multiplexed I/O & Peripheral Pin PD11 (UART, SPI) |
| H11 | PD12 | I/O | Multiplexed I/O & Peripheral Pin PD12 (UART, I2C, PWM) |
| H12 | PD13 | I/O | Multiplexed I/O & Peripheral Pin PD13 (I2C, PWM) |
| J1 | VREF+ | Analog | Multiplexed I/O & Peripheral Pin VREF+ (General) |
| J2 | VSSA | GND | Ground Reference Pin (VSSA) |
| J3 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| J10 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| J11 | PD9 | I/O | Multiplexed I/O & Peripheral Pin PD9 (UART) |
| J12 | PD10 | I/O | Multiplexed I/O & Peripheral Pin PD10 (General) |
| K1 | VDDA | Power | Power Supply Input (VDDA — 3.3V VDD (Max 4.0V)) |
| K2 | PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM) |
| K3 | VSS | GND | Ground Reference Pin (VSS) |
| K4 | PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 (ADC, PWM) |
| K5 | PB1 | I/O | Multiplexed I/O & Peripheral Pin PB1 (SPI, ADC, PWM) |
| K8 | PE12 | I/O | Multiplexed I/O & Peripheral Pin PE12 (PWM) |
| K9 | VCAP | I/O | Multiplexed I/O & Peripheral Pin VCAP (General) |
| K10 | VSS | GND | Ground Reference Pin (VSS) |
| K11 | PB14 | I/O | Multiplexed I/O & Peripheral Pin PB14 (UART, SPI) |
| K12 | PD8 | I/O | Multiplexed I/O & Peripheral Pin PD8 (UART) |
| L1 | PA3 | I/O | Multiplexed I/O & Peripheral Pin PA3 (SPI, ADC, PWM) |
| L2 | PA4 | I/O | Multiplexed I/O & Peripheral Pin PA4 (SPI, ADC) |
| L3 | PA0 | I/O | Multiplexed I/O & Peripheral Pin PA0 (UART, SPI, ADC, PWM) |
| L4 | PA7 | I/O | Multiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM) |
| L5 | PB2 | I/O | Multiplexed I/O & Peripheral Pin PB2 (SPI, PWM, RTC/CLK) |
| L6 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| L7 | VSS | GND | Ground Reference Pin (VSS) |
| L8 | PE10 | I/O | Multiplexed I/O & Peripheral Pin PE10 (PWM) |
| L9 | PE13 | I/O | Multiplexed I/O & Peripheral Pin PE13 (PWM) |
| L10 | PE15 | I/O | Multiplexed I/O & Peripheral Pin PE15 (General) |
| L11 | PB12 | I/O | Multiplexed I/O & Peripheral Pin PB12 (UART, SPI) |
| L12 | PB15 | I/O | Multiplexed I/O & Peripheral Pin PB15 (UART, SPI, PWM, RTC/CLK) |
| M1 | PA6 | I/O | Multiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM) |
| M2 | PA5 | I/O | Multiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM) |
| M3 | PC4 | I/O | Multiplexed I/O & Peripheral Pin PC4 (UART, ADC) |
| M4 | PC5 | I/O | Multiplexed I/O & Peripheral Pin PC5 (ADC) |
| M5 | PB0 | I/O | Multiplexed I/O & Peripheral Pin PB0 (UART, SPI, ADC, PWM) |
| M6 | PE7 | I/O | Multiplexed I/O & Peripheral Pin PE7 (General) |
| M7 | PE8 | I/O | Multiplexed I/O & Peripheral Pin PE8 (PWM) |
| M8 | PE9 | I/O | Multiplexed I/O & Peripheral Pin PE9 (PWM) |
| M9 | PE11 | I/O | Multiplexed I/O & Peripheral Pin PE11 (SPI) |
| M10 | PE14 | I/O | Multiplexed I/O & Peripheral Pin PE14 (PWM) |
| M11 | PB10 | I/O | Multiplexed I/O & Peripheral Pin PB10 (UART, SPI, I2C, PWM) |
| M12 | PB13 | I/O | Multiplexed I/O & Peripheral Pin PB13 (UART, SPI, I2C, PWM) |
PIN A1 PB9
I/OMultiplexed I/O & Peripheral Pin PB9 (UART, SPI, I2C)
Design note: Alt: TIM4 CH4 I3C1_SDAI2C1SDA ,_ ,_ , SPI2 NSS/I2S2_WS_ , SPI3 SCK/I2S3_CKSDMMC1CDIR_ ,_ , UART4_TXFDCAN1TX ,_ , SDMMC1 D5 DCMI D7/PSSI_D7 ,__ , EVENTOUT
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 19 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
UFBGA-100(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (19 figures · Page 1/2)
Showing 1–12 of 19 uncropped original figures for STM32H533
P63 · p63_fig01EXACT PACKAGE
P63 · p63_fig02EXACT PACKAGE
P216 · p216_fig01EXACT PACKAGE
P1 · p01_fig01881×974px
P61 · p61_fig011751×1208px
P61 · p61_fig021546×1193px
P62 · p62_fig011546×988px
P62 · p62_fig021546×1287px
P63 · p63_fig01P63
P97 · p97_fig011752×2012px
P97 · p97_fig01P97
P121 · p121_fig011546×519px
Page 1 / 2 (19 extracted figures)
Technical Specifications & Part Details (STM32H533VEI6)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:STM32H533VEI6 (UFBGA-100(7x7)) is a 100-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 0.53 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
250 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
78 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.53 mm (A1=0.20 mm)
Package family: BGA (UFBGA-100(7x7))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol100 auto-grouped pins
IPC-7351B Land Pattern100 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — STM32H533 (3)
LQFP-64(10x10) · 64P
IPC-7351B
64P10.0×10.0×1.60mmP=0.5mm
STM32H533 (LQFP-64(10x10))
UFBGA-100(7x7) · 100P
Mechanical Dimensions & Land Pattern (UFBGA-100(7x7))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.53mm · e=0.50mm
Pad Size (W × L)Level B
0.23 × 0.23 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit UFBGA-100(7x7) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32H533VEI6 (UFBGA-100(7x7))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32H533VEI6 (UFBGA-100(7x7))?
Manufactured by ST, the STM32H533VEI6 is housed in a UFBGA-100(7x7) package with 100 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (PB9: Multiplexed I/O & Peripheral Pin PB9 (UART, SPI, I2C)), A2 (PB8: Multiplexed I/O & Peripheral Pin PB8 (SPI, I2C)), A3 (BOOT0: Input-Only Pin BOOT0 (General)), A4 (PB5: Multiplexed I/O & Peripheral Pin PB5 (UART, SPI, I2C, PWM)), A5 (PB3(JTDO/ TRACESWO): Multiplexed I/O & Peripheral Pin PB3(JTDO/ TRACESWO) (SPI, I2C, SWD/JTAG)), A6 (PD6: Multiplexed I/O & Peripheral Pin PD6 (SPI, I2C)).
What are the IPC-7351B PCB Footprint dimensions for STM32H533VEI6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H533VEI6 (UFBGA-100(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 100 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H533VEI6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H533VEI6 (ST, UFBGA-100(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (100 pins) & STM32H533 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| A1 | PB9 | Digital_IO | Signal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS, SPI3_SCK. Supported peripheral buses: UART, SPI, I2C. |
| A2 | PB8 | Digital_IO | Signal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_RDY, SPI3_NSS. Supported peripheral buses: SPI, I2C. |
| A3 | BOOT0 | Digital_IO | Signal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General. |
| A4 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_MOSI, SPI3_MOSI. Supported peripheral buses: UART, SPI, I2C, PWM. |
| A5 | PB3(JTDO/ TRACESWO) | Digital_IO | Signal terminal PB3(JTDO/ TRACESWO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK, SPI3_SCK. Supported peripheral buses: SPI, I2C, SWD/JTAG. |
| A6 | PD6 | Digital_IO | Signal terminal PD6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: SPI, I2C. |
| A7 | PD4 | Digital_IO | Signal terminal PD4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: UART. |
| A8 | PD3 | Digital_IO | Signal terminal PD3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI. |
| A9 | PD1 | Digital_IO | Signal terminal PD1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: UART. |
| A10 | PC11 | Digital_IO | Signal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI, I2C. |
| A11 | PA15 (JTDI) | Digital_IO | Signal terminal PA15 (JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI, SWD/JTAG. |
| A12 | PC10 | Digital_IO | Signal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI, I2C. |
| B1 | PE0 | Digital_IO | Signal terminal PE0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: SPI. |
| B2 | PE4 | Digital_IO | Signal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_NSS. Supported peripheral buses: SPI. |
| B3 | PE3 | Digital_IO | Signal terminal PE3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General. |
| B4 | PB6 | Digital_IO | Signal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART, I2C. |
| B5 | PB4 (NJTRST) | Digital_IO | Signal terminal PB4 (NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, SPI3_MISO, SPI2_NSS. Supported peripheral buses: SPI, I2C, SWD/JTAG. |
| B6 | PD7 | Digital_IO | Signal terminal PD7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, SPI3_MISO. Supported peripheral buses: SPI, I2C. |
| B7 | PD5 | Digital_IO | Signal terminal PD5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_RDYUSART2TX. Supported peripheral buses: SPI. |
| B8 | PD2 | Digital_IO | Signal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART. |
| B9 | PD0 | Digital_IO | Signal terminal PD0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: UART. |
| B10 | PC12 | Digital_IO | Signal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: UART, SPI. |
| B11 | PA14(JTCK/ SWCLK) | Digital_IO | Signal terminal PA14(JTCK/ SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14(JTCK/ SWCLK). Supported peripheral buses: SWD/JTAG. |
| B12 | PA13(JTMS/SW DIO) | Digital_IO | Signal terminal PA13(JTMS/SW DIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13(JTMS/SW DIO). Supported peripheral buses: SWD/JTAG. |
| C1 | PE2 | Digital_IO | Signal terminal PE2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_SCK. Supported peripheral buses: SPI. |
| C2 | PE5 | Digital_IO | Signal terminal PE5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MISO. Supported peripheral buses: SPI. |
| C3 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| C4 | VCAP | Digital_IO | Signal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General. |
| C5 | PB7 | Digital_IO | Signal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MISO. Supported peripheral buses: UART, SPI, I2C. |
| C8 | VDDIO2 | Power_In | Primary positive power supply input (VDDIO2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| C9 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| C10 | VDDUSB | Power_In | Primary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| C11 | PA12 | Digital_IO | Signal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: USB, UART, SPI. |
| C12 | PA11 | Digital_IO | Signal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: USB, UART, SPI, PWM. |
| D1 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| D2 | PE6 | Digital_IO | Signal terminal PE6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MOSIFMCA22. Supported peripheral buses: SPI. |
| D3 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| D10 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| D11 | PA10 | Digital_IO | Signal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General. |
| D12 | PA9 | Digital_IO | Signal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: SPI. |
| E1 | IOE1 | Digital_IO | General Purpose Digital I/O Pin IOE1 |
| E2 | PC15 - OSC32_OUT | Digital_IO | Signal terminal PC15 - OSC32_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15 - OSC32_OUT. Supported peripheral buses: RTC/CLK. |
| E3 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK. |
| E10 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL, SPI1_RDYSPI4MOSI. Supported peripheral buses: UART, SPI, I2C, RTC/CLK. |
| E11 | PC9 | Digital_IO | Signal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: I2C, RTC/CLK. |
| E12 | PC8 | Digital_IO | Signal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: UART. |
| F1 | PH0OSC IN -_ (PH0) | Digital_IO | Signal terminal PH0OSC IN -_ (PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0OSC IN -_ (PH0). Supported peripheral buses: RTC/CLK. |
| F2 | PH1OSC OUT -_ (PH1) | Digital_IO | Signal terminal PH1OSC OUT -_ (PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1OSC OUT -_ (PH1). Supported peripheral buses: RTC/CLK. |
| F11 | PC7 | Digital_IO | Signal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: I2C. |
| F12 | PC6 | Digital_IO | Signal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: UART, PWM. |
| G1 | PC0 | Digital_IO | Signal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MISO, SPI2_RDYFMCA25. Supported peripheral buses: SPI, ADC. |
| G2 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| G11 | PD14 | Digital_IO | Signal terminal PD14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: General. |
| G12 | PD15 | Digital_IO | Signal terminal PD15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: General. |
| H1 | PC2 | Digital_IO | Signal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI, ADC. |
| H2 | PC3 | Digital_IO | Signal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, ADC. |
| H3 | PC1 | Digital_IO | Signal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI, SPI4_MOSIOCTOSPI1IO4. Supported peripheral buses: SPI, ADC. |
| H10 | PD11 | Digital_IO | Signal terminal PD11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD11. Supported peripheral buses: UART, SPI. |
| H11 | PD12 | Digital_IO | Signal terminal PD12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD12. Supported peripheral buses: UART, I2C, PWM. |
| H12 | PD13 | Digital_IO | Signal terminal PD13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: I2C, PWM. |
| J1 | VREF+ | Analog | Signal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General. |
| J2 | VSSA | GND | 0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks. |
| J3 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| J10 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |