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CH9143 (QFN-28-EP(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9143

WCHID: C2887252QFN-28-EP(4x4) · 29 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9143 (QFN-28-EP(4x4))1X32KO2X32KI3VDD_D4VSW5VCC6LED7DSR#8AT9RELOAD /BLES10FCE11DTR#12UD+13UD -14TXD15RXD29GND28CTS#27RI#26DCD#25RTS#24BLE_MOD E23SWREG_E N22VDD_A21ANT20VINTA19X32MI18X32MO17TNOW16RST#Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.225.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829E=4.00mm · Pitch e=0.50mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1X32KOI/OMultiplexed I/O & Peripheral Pin X32KO (RTC/CLK)
2X32KII/OMultiplexed I/O & Peripheral Pin X32KI (RTC/CLK)
3VDD_DPowerPower Supply Input (VDD_D — 3.3V / 5.0V Standard Logic)
4VSWI/OMultiplexed I/O & Peripheral Pin VSW (General)
5VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
6LEDI/OMultiplexed I/O & Peripheral Pin LED (General)
7DSR#I/OMultiplexed I/O & Peripheral Pin DSR# (UART)
8ATI/OMultiplexed I/O & Peripheral Pin AT (General)
9RELOAD /BLESTAI/OMultiplexed I/O & Peripheral Pin RELOAD /BLESTA (General)
10FCEI/OMultiplexed I/O & Peripheral Pin FCE (General)
11DTR#I/OMultiplexed I/O & Peripheral Pin DTR# (UART)
12UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
13UD -I/OMultiplexed I/O & Peripheral Pin UD - (General)
14TXDI/OMultiplexed I/O & Peripheral Pin TXD (UART)
15RXDI/OMultiplexed I/O & Peripheral Pin RXD (UART)
16RST#I/OMultiplexed I/O & Peripheral Pin RST# (General)
17TNOWI/OMultiplexed I/O & Peripheral Pin TNOW (General)
18X32MOI/OMultiplexed I/O & Peripheral Pin X32MO (General)
19X32MII/OMultiplexed I/O & Peripheral Pin X32MI (General)
20VINTAPowerPower Supply Input (VINTA — 3.3V / 5.0V Standard Logic)
21ANTI/OMultiplexed I/O & Peripheral Pin ANT (General)
22VDD_APowerPower Supply Input (VDD_A — 3.3V / 5.0V Standard Logic)
23SWREG_E NI/OMultiplexed I/O & Peripheral Pin SWREG_E N (General)
24BLE_MOD EI/OMultiplexed I/O & Peripheral Pin BLE_MOD E (General)
25RTS#I/OMultiplexed I/O & Peripheral Pin RTS# (UART)
26DCD#I/OMultiplexed I/O & Peripheral Pin DCD# (General)
27RI#I/OMultiplexed I/O & Peripheral Pin RI# (General)
28CTS#I/OMultiplexed I/O & Peripheral Pin CTS# (UART)
29GNDGNDGround Reference Pin (GND)
PIN 1 X32KO
I/O
Multiplexed I/O & Peripheral Pin X32KO (RTC/CLK)
Design note: Inverted output of low-frequency crystal oscillator
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9143 (WCH · QFN-28-EP(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9143 (QFN-28-EP(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9143 (QFN-28-EP(4x4)) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9143 (QFN-28-EP(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9143 (QFN-28-EP(4x4)) - 4. Package Dimensions (D×E×A)
QFN-28-EP(4x4) · 4.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9143 (QFN-28-EP(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9143 (QFN-28-EP(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for CH9143
P1 · p01_fig011602×496px
CH9143 (QFN-28-EP(4x4)) — Figure 1 Block diagram of serial communication between CH9143 USB interface and BLE
Figure 1 Block diagram of serial communication between CH9143 USB interface and BLE
P2 · p02_fig011571×527px
CH9143 (QFN-28-EP(4x4)) — Figure 3 Block diagram of serial communication between USB hosts through CH9143 in BLE master-slave mode 2. Features
Figure 3 Block diagram of serial communication between USB hosts through CH9143 in BLE master-slave mode 2. Features
P3 · p03_fig01783×783px
CH9143 (QFN-28-EP(4x4)) — 4. Package
4. Package
P3 · p03_fig01P3
CH9143 (QFN-28-EP(4x4)) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P4 · p04_fig011798×374px
CH9143 (QFN-28-EP(4x4)) — Please refer to the following table for descriptions of UUIDs. | UUID Property Description | 0xFFF1 Notify | The data received by UART is transmitted to the host through this | channel, and the host needs to enable notification. The data wi
Please refer to the following table for descriptions of UUIDs. | UUID Property Description | 0xFFF1 Notify | The data received by UART is transmitted to the host through this | channel, and the host needs to enable notification. The data wi

Technical Specifications & Part Details (CH9143)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9143 (QFN-28-EP(4x4)) is a 28-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, UART, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-28-EP(4x4))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, UART, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 2.70×2.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-28-EP(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-28-EP(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9143 (QFN-28-EP(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9143 (QFN-28-EP(4x4))?

Manufactured by WCH, the CH9143 is housed in a QFN-28-EP(4x4) package with 29 pins and a 0.50 mm lead pitch. Key pins include: 1 (X32KO: Multiplexed I/O & Peripheral Pin X32KO (RTC/CLK)), 2 (X32KI: Multiplexed I/O & Peripheral Pin X32KI (RTC/CLK)), 3 (VDD_D: Power Supply Input (VDD_D — 3.3V / 5.0V Standard Logic)), 4 (VSW: Multiplexed I/O & Peripheral Pin VSW (General)), 5 (VCC: Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)), 6 (LED: Multiplexed I/O & Peripheral Pin LED (General)).

What are the IPC-7351B PCB Footprint dimensions for CH9143?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9143 (QFN-28-EP(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 2.70 × 2.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9143?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9143 (WCH, QFN-28-EP(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & CH9143 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1X32KODigital_IOSignal terminal X32KO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32KO. Supported peripheral buses: RTC/CLK.
2X32KIDigital_IOSignal terminal X32KI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32KI. Supported peripheral buses: RTC/CLK.
3VDD_DPower_InPrimary positive power supply input (VDD_D) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4VSWDigital_IOSignal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: General.
5VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
6LEDDigital_IOSignal terminal LED (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED. Supported peripheral buses: General.
7DSR#Digital_IOSignal terminal DSR# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR#. Supported peripheral buses: UART.
8ATDigital_IOSignal terminal AT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AT. Supported peripheral buses: General.
9RELOAD /BLESTADigital_IOSignal terminal RELOAD /BLESTA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RELOAD /BLESTA. Supported peripheral buses: General.
10FCEDigital_IOSignal terminal FCE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: FCE. Supported peripheral buses: General.
11DTR#Digital_IOSignal terminal DTR# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR#. Supported peripheral buses: UART.
12UD+Digital_IOSignal terminal UD+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
13UD -Digital_IOSignal terminal UD - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD -. Supported peripheral buses: General.
14TXDDigital_IOSignal terminal TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
15RXDDigital_IOSignal terminal RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART.
16RST#Digital_IOSignal terminal RST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST#. Supported peripheral buses: General.
17TNOWDigital_IOSignal terminal TNOW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW. Supported peripheral buses: General.
18X32MODigital_IOSignal terminal X32MO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MO. Supported peripheral buses: General.
19X32MIDigital_IOSignal terminal X32MI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MI. Supported peripheral buses: General.
20VINTAPower_InPrimary positive power supply input (VINTA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
21ANTRF_50OhmSignal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General.
22VDD_APower_InPrimary positive power supply input (VDD_A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
23SWREG_E NDigital_IOSignal terminal SWREG_E N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SWREG_E N. Supported peripheral buses: General.
24BLE_MOD EDigital_IOSignal terminal BLE_MOD E (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BLE_MOD E. Supported peripheral buses: General.
25RTS#Digital_IOSignal terminal RTS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS#. Supported peripheral buses: UART.
26DCD#Digital_IOSignal terminal DCD# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD#. Supported peripheral buses: General.
27RI#Digital_IOSignal terminal RI# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI#. Supported peripheral buses: General.
28CTS#Digital_IOSignal terminal CTS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS#. Supported peripheral buses: UART.
29GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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