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ESP32-C3FN4 (QFN-32-EP(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

ESP32-C3FN4

ESPRESSIFID: C2848860QFN-32-EP(5x5) · 33 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ESP32-C3FN4 (QFN-32-EP(5x5))1LNA_IN2VDD3P33VDD3P34XTAL_32KP_5XTAL_32KN_6GPIO27CHIP_EN8GPIO39MTMS10MTDI11VDD3P3_RTC12MTCK13MTDO14GPIO815GPIO916GPIO1017VDD3P3_CPU33GND32VDDA31VDDA30XTAL_P29XTAL_N28U0TXD27U0RXD26GPIO1925GPIO1824SPIQ23SPID22SPICLK21SPICS020SPIWP19SPIHD188_VDDSPI 9Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.827.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233E=5.00mm · Pitch e=0.50mmD=5.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1LNA_INI/OMultiplexed I/O & Peripheral Pin LNA_IN (General)
2VDD3P3PowerPower Supply Input (VDD3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V))
3VDD3P3PowerPower Supply Input (VDD3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V))
4XTAL_32KP_I/OMultiplexed I/O & Peripheral Pin XTAL_32KP_ (RTC/CLK)
5XTAL_32KN_I/OMultiplexed I/O & Peripheral Pin XTAL_32KN_ (RTC/CLK)
6GPIO2I/OMultiplexed I/O & Peripheral Pin GPIO2 (General)
7CHIP_ENI/OMultiplexed I/O & Peripheral Pin CHIP_EN (General)
8GPIO3I/OMultiplexed I/O & Peripheral Pin GPIO3 (General)
9MTMSI/OMultiplexed I/O & Peripheral Pin MTMS (SWD/JTAG)
10MTDII/OMultiplexed I/O & Peripheral Pin MTDI (SWD/JTAG)
11VDD3P3_RTCPowerPower Supply Input (VDD3P3_RTC — 3.3V VDD3P3 (3.0V ~ 3.6V))
12MTCKI/OMultiplexed I/O & Peripheral Pin MTCK (SWD/JTAG)
13MTDOI/OMultiplexed I/O & Peripheral Pin MTDO (SWD/JTAG)
14GPIO8I/OMultiplexed I/O & Peripheral Pin GPIO8 (General)
15GPIO9I/OMultiplexed I/O & Peripheral Pin GPIO9 (General)
16GPIO10I/OMultiplexed I/O & Peripheral Pin GPIO10 (General)
17VDD3P3_CPUPowerPower Supply Input (VDD3P3_CPU — 3.3V VDD3P3 (3.0V ~ 3.6V))
188_VDDSPI 9PowerPower Supply Input (8_VDDSPI 9 — 3.3V VDD3P3 (3.0V ~ 3.6V))
19SPIHDI/OMultiplexed I/O & Peripheral Pin SPIHD (SPI)
20SPIWPI/OMultiplexed I/O & Peripheral Pin SPIWP (SPI)
21SPICS0I/OMultiplexed I/O & Peripheral Pin SPICS0 (SPI)
22SPICLKI/OMultiplexed I/O & Peripheral Pin SPICLK (SPI)
23SPIDI/OMultiplexed I/O & Peripheral Pin SPID (SPI)
24SPIQI/OMultiplexed I/O & Peripheral Pin SPIQ (SPI)
25GPIO18I/OMultiplexed I/O & Peripheral Pin GPIO18 (General)
26GPIO19I/OMultiplexed I/O & Peripheral Pin GPIO19 (General)
27U0RXDI/OMultiplexed I/O & Peripheral Pin U0RXD (UART)
28U0TXDI/OMultiplexed I/O & Peripheral Pin U0TXD (UART)
29XTAL_NI/OMultiplexed I/O & Peripheral Pin XTAL_N (RTC/CLK)
30XTAL_PI/OMultiplexed I/O & Peripheral Pin XTAL_P (RTC/CLK)
31VDDAPowerPower Supply Input (VDDA — 3.3V VDD3P3 (3.0V ~ 3.6V))
32VDDAPowerPower Supply Input (VDDA — 3.3V VDD3P3 (3.0V ~ 3.6V))
33GNDGNDGround Reference Pin (GND)
PIN 1 LNA_IN
I/O
Multiplexed I/O & Peripheral Pin LNA_IN (General)
Design note: Signal terminal LNA_IN (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: LNA_IN. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ESP32-C3FN4 (ESPRESSIF · QFN-32-EP(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ESP32-C3FN4 (QFN-32-EP(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ESP32-C3FN4 (QFN-32-EP(5x5)) - 2. Standard Pinout (Top View)
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ESP32-C3FN4 (QFN-32-EP(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ESP32-C3FN4 (QFN-32-EP(5x5)) - 4. Package Dimensions (D×E×A)
QFN-32-EP(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
ESP32-C3FN4 (QFN-32-EP(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
ESP32-C3FN4 (QFN-32-EP(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for ESP32-C3FN4
P62 · p62_fig01EXACT PACKAGE
ESP32-C3FN4 (QFN-32-EP(5x5)) — Figure 7-1. QFN32 (5×5 mm) Package
Figure 7-1. QFN32 (5×5 mm) Package
P1 · p01_fig01336×313px
ESP32-C3FN4 (QFN-32-EP(5x5)) — S) ESPRESSIF
S) ESPRESSIF
P2 · p02_fig011648×1264px
ESP32-C3FN4 (QFN-32-EP(5x5)) — The functional block diagram of the SoC is shown below.
The functional block diagram of the SoC is shown below.
P12 · p12_fig011710×1725px
ESP32-C3FN4 (QFN-32-EP(5x5)) — Figure 2-1. ESP32-C3 Pin Layout (Top View)
Figure 2-1. ESP32-C3 Pin Layout (Top View)
P12 · p12_fig02896×276px
ESP32-C3FN4 (QFN-32-EP(5x5)) — 5
5
P12 · p12_fig01P12
ESP32-C3FN4 (QFN-32-EP(5x5)) — Datasheet Page 12 (p12_fig01)
Datasheet Page 12 (p12_fig01)

Technical Specifications & Part Details (ESP32-C3FN4)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Wireless Wi-Fi / Bluetooth LE SoC Module
Detailed Overview:ESP32-C3FN4 (QFN-32-EP(5x5)) is a 32-pin wireless wi-fi / bluetooth le soc module featuring a 5.00 × 5.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Wi-Fi, Bluetooth / BLE, USB, UART, I2C, I2S, ADC, PWM, JTAG / SWD, RTC/CLK, SPI, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_TX(peak) ≈ 310 mA @ 3.3V | Deep-Sleep ≈ 10 µA | I_GPIO(max) = 40 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-32-EP(5x5))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, Bluetooth / BLE, USB, UART, I2C, I2S, ADC, PWM, JTAG / SWD, RTC/CLK, SPI, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (MTDI, MTDO): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol33 auto-grouped pins
OK
IPC-7351B Land Pattern33 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 3.70×3.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-32-EP(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1, C2
BOM
22µF (or 10µF) X5R + 100nF X7R
0805 + 0402
3V3 supply decoupling for ~500mA Wi-Fi TX bursts — place closest to 3V3 pin; supply must deliver >= 600mA.
R_en + C_en
BOM
R = 10kΩ to 3V3 + C = 1µF to GND
0402 / 0603
Power-On Reset RC delay at EN (CHIP_PU) — 1µF capacitor at EN is REQUIRED for reliable cold boot.
R_boot + SW1
BOM
10kΩ Pull-up + BOOT button
0402 + SMD
Firmware boot-mode strap (IO0 on ESP32/S2/S3, IO9 on ESP32-C3) — on C3 pull IO8 high via 10kΩ for UART/USB download.
D_esd
BOM
USBLC6-2SC6 / LESD5D5.0CT1G
SOT-23-6 / SOD-523
ESD surge protection on USB D+/D- — place right next to USB Type-C connector before IO18/IO19/IO20.
ESP32-S3-MINI-1-N8 / 1U-N4R2
Espressif
100% Drop-inSame 15.4×15.4mm 65-pad footprint as ESP32-S2-MINI-2 — verify USB GPIO 19/20 pin mapping.

Technical Frequently Asked Questions (FAQ) — ESP32-C3FN4 (QFN-32-EP(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ESP32-C3FN4 (QFN-32-EP(5x5))?

Manufactured by ESPRESSIF, the ESP32-C3FN4 is housed in a QFN-32-EP(5x5) package with 33 pins and a 0.50 mm lead pitch. Key pins include: 1 (LNA_IN: Multiplexed I/O & Peripheral Pin LNA_IN (General)), 2 (VDD3P3: Power Supply Input (VDD3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V))), 3 (VDD3P3: Power Supply Input (VDD3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V))), 4 (XTAL_32KP_: Multiplexed I/O & Peripheral Pin XTAL_32KP_ (RTC/CLK)), 5 (XTAL_32KN_: Multiplexed I/O & Peripheral Pin XTAL_32KN_ (RTC/CLK)), 6 (GPIO2: Multiplexed I/O & Peripheral Pin GPIO2 (General)).

What are the IPC-7351B PCB Footprint dimensions for ESP32-C3FN4?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ESP32-C3FN4 (QFN-32-EP(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 3.70 × 3.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ESP32-C3FN4?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ESP32-C3FN4 (ESPRESSIF, QFN-32-EP(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & ESP32-C3FN4 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1LNA_INRF_50OhmSignal terminal LNA_IN (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: LNA_IN. Supported peripheral buses: General.
2VDD3P3Power_InPrimary positive power supply input (VDD3P3) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
3VDD3P3Power_InPrimary positive power supply input (VDD3P3) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
4XTAL_32KP_Digital_IOSignal terminal XTAL_32KP_ (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: XTAL_32KP_. Supported peripheral buses: RTC/CLK.
5XTAL_32KN_Digital_IOSignal terminal XTAL_32KN_ (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: XTAL_32KN_. Supported peripheral buses: RTC/CLK.
6GPIO2Digital_IOSignal terminal GPIO2 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO2. Supported peripheral buses: General.
7CHIP_ENDigital_IOSignal terminal CHIP_EN (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: CHIP_EN. Supported peripheral buses: General.
8GPIO3Digital_IOSignal terminal GPIO3 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO3. Supported peripheral buses: General.
9MTMSDigital_IOSignal terminal MTMS (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTMS. Supported peripheral buses: SWD/JTAG.
10MTDIDigital_IOSignal terminal MTDI (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTDI. Supported peripheral buses: SWD/JTAG.
11VDD3P3_RTCPower_InPrimary positive power supply input (VDD3P3_RTC) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
12MTCKDigital_IOSignal terminal MTCK (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTCK. Supported peripheral buses: SWD/JTAG.
13MTDODigital_IOSignal terminal MTDO (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTDO. Supported peripheral buses: SWD/JTAG.
14GPIO8Digital_IOSignal terminal GPIO8 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO8. Supported peripheral buses: General.
15GPIO9Digital_IOSignal terminal GPIO9 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO9. Supported peripheral buses: General.
16GPIO10Digital_IOSignal terminal GPIO10 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO10. Supported peripheral buses: General.
17VDD3P3_CPUPower_InPrimary positive power supply input (VDD3P3_CPU) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
188_VDDSPI 9Power_InPrimary positive power supply input (8_VDDSPI 9) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
19SPIHDDigital_IOSignal terminal SPIHD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIHD. Supported peripheral buses: SPI.
20SPIWPDigital_IOSignal terminal SPIWP (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIWP. Supported peripheral buses: SPI.
21SPICS0Digital_IOSignal terminal SPICS0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPICS0. Supported peripheral buses: SPI.
22SPICLKDigital_IOSignal terminal SPICLK (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPICLK. Supported peripheral buses: SPI.
23SPIDDigital_IOSignal terminal SPID (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPID. Supported peripheral buses: SPI.
24SPIQDigital_IOSignal terminal SPIQ (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIQ. Supported peripheral buses: SPI.
25GPIO18Digital_IOSignal terminal GPIO18 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO18. Supported peripheral buses: General.
26GPIO19Digital_IOSignal terminal GPIO19 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO19. Supported peripheral buses: General.
27U0RXDDigital_IOSignal terminal U0RXD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: U0RXD. Supported peripheral buses: UART.
28U0TXDDigital_IOSignal terminal U0TXD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: U0TXD. Supported peripheral buses: UART.
29XTAL_NDigital_IOSignal terminal XTAL_N (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: XTAL_N. Supported peripheral buses: RTC/CLK.
30XTAL_PDigital_IOSignal terminal XTAL_P (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: XTAL_P. Supported peripheral buses: RTC/CLK.
31VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
32VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
33GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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