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STM32WB30CEU5A (UFQFPN-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32WB30CEU5A

STID: C2846828UFQFPN-48(7x7) · 49 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32WB30CEU5A (UFQFPN-48(7x7))1VBAT2PC14OSC32 IN3PC15OSC32 OU4PH3BOOT0 -5PB86PB97NRST8VDDA9PA010PA111PA212PA313PA414PA515PA616PA717PA818PA919PB220VDD21RF122VSSRF23VDDRF24OSC_OUT25OSC_IN49PAD48VDD47PB746PB645PB544PB4 (NJTRST)43PB3 (JTDO)42PA15 (JTDI)41PA14 (JTCK S40VDD39PA13(JTMS SW38PA1237PA1136PA1035VDD34VDD33VDD32VSS31VDD30PE429PB128PB027AT126AT0Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.838.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849E=7.00mm · Pitch e=0.50mmD=7.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
2PC14OSC32 IN -_I/OMultiplexed I/O & Peripheral Pin PC14OSC32 IN -_ (RTC/CLK)
3PC15OSC32 OUT -_I/OMultiplexed I/O & Peripheral Pin PC15OSC32 OUT -_ (RTC/CLK)
4PH3BOOT0 -I/OMultiplexed I/O & Peripheral Pin PH3BOOT0 - (General)
5PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C)
6PB9I/OMultiplexed I/O & Peripheral Pin PB9 (I2C)
7NRSTISystem Enable & Hardware Reset (NRST)
8VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
9PA0I/OMultiplexed I/O & Peripheral Pin PA0 (ADC, RTC/CLK)
10PA1I/OMultiplexed I/O & Peripheral Pin PA1 (I2C, ADC)
11PA2I/OMultiplexed I/O & Peripheral Pin PA2 (ADC)
12PA3I/OMultiplexed I/O & Peripheral Pin PA3 (ADC, PWM)
13PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI, ADC)
14PA5I/OMultiplexed I/O & Peripheral Pin PA5 (ADC)
15PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
16PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC)
17PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, ADC, RTC/CLK)
18PA9I/OMultiplexed I/O & Peripheral Pin PA9 (I2C, ADC)
19PB2I/OMultiplexed I/O & Peripheral Pin PB2 (RTC/CLK)
20VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
21RF1I/OMultiplexed I/O & Peripheral Pin RF1 (General)
22VSSRFGNDGround Reference Pin (VSSRF)
23VDDRFPowerPower Supply Input (VDDRF — 3.3V VDD (Max 4.0V))
24OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
25OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
26AT0I/OMultiplexed I/O & Peripheral Pin AT0 (General)
27AT1I/OMultiplexed I/O & Peripheral Pin AT1 (General)
28PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
29PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
30PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
31VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
32VSSGNDGround Reference Pin (VSS)
33VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
34VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
35VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
36PA10I/OMultiplexed I/O & Peripheral Pin PA10 (I2C)
37PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART)
38PA12I/OMultiplexed I/O & Peripheral Pin PA12 (SPI)
39PA13(JTMS SWDIO)_I/OMultiplexed I/O & Peripheral Pin PA13(JTMS SWDIO)_ (SWD/JTAG)
40VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
41PA14 (JTCK SWCLK)_I/OMultiplexed I/O & Peripheral Pin PA14 (JTCK SWCLK)_ (I2C, SWD/JTAG)
42PA15 (JTDI)I/OMultiplexed I/O & Peripheral Pin PA15 (JTDI) (SPI, SWD/JTAG)
43PB3 (JTDO)I/OMultiplexed I/O & Peripheral Pin PB3 (JTDO) (SPI, SWD/JTAG)
44PB4 (NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4 (NJTRST) (UART, SPI, SWD/JTAG)
45PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, I2C)
46PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C, RTC/CLK)
47PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART)
48VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
49PADI/OMultiplexed I/O & Peripheral Pin PAD (General)
PIN 1 VBAT
Power
Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32WB30CEU5A (ST · UFQFPN-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32WB30CEU5A (UFQFPN-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32WB30CEU5A (UFQFPN-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32WB30CEU5A (UFQFPN-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32WB30CEU5A (UFQFPN-48(7x7)) - 4. Package Dimensions (D×E×A)
UFQFPN-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32WB30CEU5A (UFQFPN-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32WB30CEU5A (UFQFPN-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for STM32WB30
P46 · p46_fig01EXACT PACKAGE
STM32WB30CEU5A (UFQFPN-48(7x7)) — Figure 8. STM32WB50CG and STM32WB30CE UFQFPN48 pinout(1)(2)
Figure 8. STM32WB50CG and STM32WB30CE UFQFPN48 pinout(1)(2)
P111 · p111_fig01EXACT PACKAGE
STM32WB30CEU5A (UFQFPN-48(7x7)) — Figure 27. UFQFPN48 outline
Figure 27. UFQFPN48 outline
P112 · p112_fig01EXACT PACKAGE
STM32WB30CEU5A (UFQFPN-48(7x7)) — Figure 28. UFQFPN48 recommended footprint
Figure 28. UFQFPN48 recommended footprint
P1 · p01_fig01881×549px
STM32WB30CEU5A (UFQFPN-48(7x7)) — STM32WB50CG STM32WB30CE Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4
STM32WB50CG STM32WB30CE Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4
P22 · p22_fig011548×1422px
STM32WB30CEU5A (UFQFPN-48(7x7)) — Figure 4. External components for the RF part
Figure 4. External components for the RF part
P46 · p46_fig01P46
STM32WB30CEU5A (UFQFPN-48(7x7)) — Datasheet Page 46 (p46_fig01)
Datasheet Page 46 (p46_fig01)
P54 · p54_fig011546×1500px
STM32WB30CEU5A (UFQFPN-48(7x7)) — Figure 11. Power supply scheme
Figure 11. Power supply scheme
P54 · p54_fig01P54
STM32WB30CEU5A (UFQFPN-48(7x7)) — Datasheet Page 54 (p54_fig01)
Datasheet Page 54 (p54_fig01)
P79 · p79_fig011546×702px
STM32WB30CEU5A (UFQFPN-48(7x7)) — Figure 16. Typical application with a 32.768 kHz crystal
Figure 16. Typical application with a 32.768 kHz crystal
P103 · p103_fig011546×815px
STM32WB30CEU5A (UFQFPN-48(7x7)) — Figure 22. ADC accuracy characteristics
Figure 22. ADC accuracy characteristics
P103 · p103_fig021546×640px
STM32WB30CEU5A (UFQFPN-48(7x7)) — Figure 23. Typical connection diagram using the ADC
Figure 23. Typical connection diagram using the ADC
P111 · p111_fig01P111
STM32WB30CEU5A (UFQFPN-48(7x7)) — Datasheet Page 111 (p111_fig01)
Datasheet Page 111 (p111_fig01)
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (STM32WB30CEU5A)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32WB30CEU5A (UFQFPN-48(7x7)) is a 48-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 0.55 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across 10 °C to +85 °C with integrated Bluetooth / BLE, UART, SPI, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
10 °C to +85 °C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
28 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.55 mm (A1=0.04 mm)
Package family: QFN (UFQFPN-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, UART, SPI, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 5.60×5.60mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFQFPN-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.55mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 0.55 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFQFPN-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32WB30CEU5A (UFQFPN-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32WB30CEU5A (UFQFPN-48(7x7))?

Manufactured by ST, the STM32WB30CEU5A is housed in a UFQFPN-48(7x7) package with 49 pins and a 0.50 mm lead pitch. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC14OSC32 IN -_: Multiplexed I/O & Peripheral Pin PC14OSC32 IN -_ (RTC/CLK)), 3 (PC15OSC32 OUT -_: Multiplexed I/O & Peripheral Pin PC15OSC32 OUT -_ (RTC/CLK)), 4 (PH3BOOT0 -: Multiplexed I/O & Peripheral Pin PH3BOOT0 - (General)), 5 (PB8: Multiplexed I/O & Peripheral Pin PB8 (I2C)), 6 (PB9: Multiplexed I/O & Peripheral Pin PB9 (I2C)).

What are the IPC-7351B PCB Footprint dimensions for STM32WB30CEU5A?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32WB30CEU5A (UFQFPN-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 5.60 × 5.60 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32WB30CEU5A?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32WB30CEU5A (ST, UFQFPN-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & STM32WB30 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
2PC14OSC32 IN -_Digital_IOSignal terminal PC14OSC32 IN -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14OSC32 IN -_. Supported peripheral buses: RTC/CLK.
3PC15OSC32 OUT -_Digital_IOSignal terminal PC15OSC32 OUT -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15OSC32 OUT -_. Supported peripheral buses: RTC/CLK.
4PH3BOOT0 -Digital_IOSignal terminal PH3BOOT0 - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH3BOOT0 -. Supported peripheral buses: General.
5PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: I2C.
6PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDAIROUT. Supported peripheral buses: I2C.
7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
9PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: ADC, RTC/CLK.
10PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: I2C, ADC.
11PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: ADC.
12PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: ADC, PWM.
13PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSSLPTIM2OUT. Supported peripheral buses: SPI, ADC.
14PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: ADC.
15PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOTIM16CH1. Supported peripheral buses: SPI, ADC.
16PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSITIM17CH1. Supported peripheral buses: SPI, ADC.
17PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, ADC, RTC/CLK.
18PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: I2C, ADC.
19PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: RTC/CLK.
20VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
21RF1RF_50OhmSignal terminal RF1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: RF1. Supported peripheral buses: General.
22VSSRFGND0V electrical ground return terminal (VSSRF) for internal core logic, I/O drivers, and analog sub-blocks.
23VDDRFPower_InPrimary positive power supply input (VDDRF) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
24OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
25OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
26AT0Digital_IOSignal terminal AT0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: AT0. Supported peripheral buses: General.
27AT1Digital_IOSignal terminal AT1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: AT1. Supported peripheral buses: General.
28PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
29PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
30PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
31VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
32VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
33VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
34VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
35VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
36PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: I2C.
37PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: UART.
38PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSIUSART1RTS. Supported peripheral buses: SPI.
39PA13(JTMS SWDIO)_Digital_IOSignal terminal PA13(JTMS SWDIO)_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13(JTMS SWDIO)_. Supported peripheral buses: SWD/JTAG.
40VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
41PA14 (JTCK SWCLK)_Digital_IOSignal terminal PA14 (JTCK SWCLK)_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14 (JTCK SWCLK)_. Supported peripheral buses: I2C, SWD/JTAG.
42PA15 (JTDI)Digital_IOSignal terminal PA15 (JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: SPI, SWD/JTAG.
43PB3 (JTDO)Digital_IOSignal terminal PB3 (JTDO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCKUSART1RTS. Supported peripheral buses: SPI, SWD/JTAG.
44PB4 (NJTRST)Digital_IOSignal terminal PB4 (NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, SWD/JTAG.
45PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: UART, I2C.
46PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: I2C, RTC/CLK.
47PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: UART.
48VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
49PADDigital_IOSignal terminal PAD (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PAD. Supported peripheral buses: General.
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