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CH9329 (SOP-16) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9329

WCHID: C2838834SOP-16 · 16 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9329 (SOP-16)1ACT#2MODE03MODE14CFG05CFG16RST7TXD8RXD16V3315VCC14GND13UD-12UD+11SET10DEF9UPGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.215.210.25.10-5.1-10.2-15.2mm
2. 2D FOOTPRINT
12345678910111213141516E=3.90mm · Pitch e=1.27mmD=9.90mm-6-5-4-3-2-1012345676543210-1-2-3-4-5-6-7mm
3. 3D CAD MODEL
Package Body: 3.90mm × 9.90mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (16/16)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1ACT#I/OMultiplexed I/O & Peripheral Pin ACT# (General)
2MODE0I/OMultiplexed I/O & Peripheral Pin MODE0 (General)
3MODE1I/OMultiplexed I/O & Peripheral Pin MODE1 (General)
4CFG0I/OMultiplexed I/O & Peripheral Pin CFG0 (General)
5CFG1I/OMultiplexed I/O & Peripheral Pin CFG1 (General)
6RSTI/OMultiplexed I/O & Peripheral Pin RST (General)
7TXDI/OMultiplexed I/O & Peripheral Pin TXD (UART)
8RXDI/OMultiplexed I/O & Peripheral Pin RXD (UART)
9UPI/OMultiplexed I/O & Peripheral Pin UP (General)
10DEFI/OMultiplexed I/O & Peripheral Pin DEF (General)
11SETI/OMultiplexed I/O & Peripheral Pin SET (General)
12UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
13UD-I/OMultiplexed I/O & Peripheral Pin UD- (USB)
14GNDGNDGround Reference Pin (GND)
15VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
16V33PowerPower Supply Input (V33 — 3.3V / 5.0V Standard Logic)
PIN 1 ACT#
I/O
Multiplexed I/O & Peripheral Pin ACT# (General)
Design note: Signal terminal ACT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ACT#. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9329 (WCH · SOP-16)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9329 (SOP-16) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9329 (SOP-16) - 2. Standard Pinout (Top View)
True package pinout (16 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9329 (SOP-16) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9329 (SOP-16) - 4. Package Dimensions (D×E×A)
SOP-16 · 3.90×9.90mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9329 (SOP-16) - 5. Recommended Land Pattern
IPC-7351B Footprint (16 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9329 (SOP-16) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH9329
P1 · p01_fig011272×392px
CH9329 (SOP-16) — 2. Features
2. Features
P2 · p02_fig01744×692px
CH9329 (SOP-16) — Package Body size Lead pitch Description Part No.
Package Body size Lead pitch Description Part No.
P2 · p02_fig01P2
CH9329 (SOP-16) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P4 · p04_fig011708×1219px
CH9329 (SOP-16) — Description of serial communication mode configuration:
Description of serial communication mode configuration:
P4 · p04_fig021746×1414px
CH9329 (SOP-16) — If MODE0 and MODE1 pins are suspended, the chip works in MODE0 by default.
If MODE0 and MODE1 pins are suspended, the chip works in MODE0 by default.
P7 · p07_fig011451×946px
CH9329 (SOP-16) — u ta Lo | O.1uF ~[—O.1uF — ee = sot# 1) gong vg | _ 03 «tl 7 3] hope. GND _— 1 MODE! GND [rma 4 3) CRCe UD- opt 37] 2 2 cra up+ | + p+ RST SET GND ea z TxD DEF a GND RAD UP GND CH9329 => USB P2 voc LEDI 1 ACTH Rl 1 rsp 33 2 3K3 3 SED a 44 L
u ta Lo | O.1uF ~[—O.1uF — ee = sot# 1) gong vg | _ 03 «tl 7 3] hope. GND _— 1 MODE! GND [rma 4 3) CRCe UD- opt 37] 2 2 cra up+ | + p+ RST SET GND ea z TxD DEF a GND RAD UP GND CH9329 => USB P2 voc LEDI 1 ACTH Rl 1 rsp 33 2 3K3 3 SED a 44 L
P7 · p07_fig01P7
CH9329 (SOP-16) — Datasheet Page 7 (p07_fig01)
Datasheet Page 7 (p07_fig01)
P9 · p09_fig01EXACT PACKAGE
CH9329 (SOP-16) — 7.1 QFN32 封装 [QFN-32(4x4)]
7.1 QFN32 封装 [QFN-32(4x4)]

Technical Specifications & Part Details (CH9329)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9329 (SOP-16) is a 16-pin standard electronic & interconnect component featuring a 9.90 × 3.90 × 1.75 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
24MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
9.90 × 3.90 × 1.75 mm (A1=0.15 mm)
Package family: SOP (SOP-16)
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol16 auto-grouped pins
OK
IPC-7351B Land Pattern16 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — CH9329 (2)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (SOP-16)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
9.90 × 3.90 mm
Height (A) & Pitch (e)IPC-7351B
A=1.75mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.55 mm
Pins / Total PadsTopology
16P / 16Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOP-16
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9329 (SOP-16)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9329 (SOP-16)?

Manufactured by WCH, the CH9329 is housed in a SOP-16 package with 16 pins and a 1.27 mm lead pitch. Key pins include: 1 (ACT#: Multiplexed I/O & Peripheral Pin ACT# (General)), 2 (MODE0: Multiplexed I/O & Peripheral Pin MODE0 (General)), 3 (MODE1: Multiplexed I/O & Peripheral Pin MODE1 (General)), 4 (CFG0: Multiplexed I/O & Peripheral Pin CFG0 (General)), 5 (CFG1: Multiplexed I/O & Peripheral Pin CFG1 (General)), 6 (RST: Multiplexed I/O & Peripheral Pin RST (General)).

What are the IPC-7351B PCB Footprint dimensions for CH9329?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9329 (SOP-16) has a nominal body envelope of 3.90 × 9.90 mm, pitch e = 1.27 mm, and 16 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9329?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9329 (WCH, SOP-16) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (16 pins) & CH9329 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1ACT#Digital_IOSignal terminal ACT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ACT#. Supported peripheral buses: General.
2MODE0Digital_IOSignal terminal MODE0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MODE0. Supported peripheral buses: General.
3MODE1Digital_IOSignal terminal MODE1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MODE1. Supported peripheral buses: General.
4CFG0Digital_IOSignal terminal CFG0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG0. Supported peripheral buses: General.
5CFG1Digital_IOSignal terminal CFG1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG1. Supported peripheral buses: General.
6RSTDigital_IOSignal terminal RST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST. Supported peripheral buses: General.
7TXDDigital_IOSignal terminal TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
8RXDDigital_IOSignal terminal RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART.
9UPDigital_IOSignal terminal UP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP. Supported peripheral buses: General.
10DEFDigital_IOSignal terminal DEF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DEF. Supported peripheral buses: General.
11SETDigital_IOSignal terminal SET (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SET. Supported peripheral buses: General.
12UD+Digital_IOSignal terminal UD+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
13UD-Digital_IOSignal terminal UD- (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB.
14GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
15VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
16V33Power_InPrimary positive power supply input (V33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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