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CH9329F (QFN-32(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9329F

WCHID: C51139783QFN-32(4x4) · 33 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9329F (QFN-32(4x4))1IO12NC3NC4NC5NC6VDD337UD-8UD+9IO410DEF11SET12UD+13UD -14GND15VCC16V3317GPIO433GND32GPIO331GPIO230GPIO129GPIO028CFG127CFG026TXD25RXD24TNOW23CTS22RTS/FLC_EN21DEF20SET19VIO18TP_ENGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.227.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233E=4.00mm · Pitch e=0.40mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1IO1I/OGeneral Purpose Digital I/O Pin IO1
2NCI/OMultiplexed I/O & Peripheral Pin NC (General)
3NCI/OMultiplexed I/O & Peripheral Pin NC (General)
4NCI/OMultiplexed I/O & Peripheral Pin NC (General)
5NCI/OMultiplexed I/O & Peripheral Pin NC (General)
6VDD33PowerPower Supply Input (VDD33 — 3.3V to 5V)
7UD-I/OMultiplexed I/O & Peripheral Pin UD- (USB)
8UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
9IO4I/OGPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10DEFI/OMultiplexed I/O & Peripheral Pin DEF (General)
11SETI/OMultiplexed I/O & Peripheral Pin SET (General)
12UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
13UD -I/OMultiplexed I/O & Peripheral Pin UD - (General)
14GNDGNDGround Reference Pin (GND)
15VCCPowerPower Supply Input (VCC — 3.3V to 5V)
16V33PowerPower Supply Input (V33 — 3.3V to 5V)
17GPIO4I/OMultiplexed I/O & Peripheral Pin GPIO4 (General)
18TP_ENI/OMultiplexed I/O & Peripheral Pin TP_EN (General)
19VIOI/OMultiplexed I/O & Peripheral Pin VIO (General)
20SETI/OMultiplexed I/O & Peripheral Pin SET (General)
21DEFI/OMultiplexed I/O & Peripheral Pin DEF (General)
22RTS/FLC_ENI/OMultiplexed I/O & Peripheral Pin RTS/FLC_EN (UART)
23CTSI/OMultiplexed I/O & Peripheral Pin CTS (UART)
24TNOWI/OMultiplexed I/O & Peripheral Pin TNOW (General)
25RXDI/OMultiplexed I/O & Peripheral Pin RXD (UART)
26TXDI/OMultiplexed I/O & Peripheral Pin TXD (UART)
27CFG0I/OMultiplexed I/O & Peripheral Pin CFG0 (General)
28CFG1I/OMultiplexed I/O & Peripheral Pin CFG1 (General)
29GPIO0I/OMultiplexed I/O & Peripheral Pin GPIO0 (General)
30GPIO1I/OMultiplexed I/O & Peripheral Pin GPIO1 (General)
31GPIO2I/OMultiplexed I/O & Peripheral Pin GPIO2 (General)
32GPIO3I/OMultiplexed I/O & Peripheral Pin GPIO3 (General)
33GNDGNDGround Reference Pin (GND)
PIN 1 IO1
I/O
General Purpose Digital I/O Pin IO1
Design note: 3.3V logic domain (3.6V absolute max), 40mA max drive current.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9329F (WCH · QFN-32(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9329F (QFN-32(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9329F (QFN-32(4x4)) - 2. Standard Pinout (Top View)
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9329F (QFN-32(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9329F (QFN-32(4x4)) - 4. Package Dimensions (D×E×A)
QFN-32(4x4) · 4.00×4.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9329F (QFN-32(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9329F (QFN-32(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH9329
P2 · p02_fig01EXACT PACKAGE
CH9329F (QFN-32(4x4)) — 2、CH9329F 的0#引脚是QFN 封装的底板，是必要连接。 3、优选CH9329F，性能更优，速度更快，功能更齐全。 4、本手册中当CH9329 与CH9329F 并列或先后出现时，CH9329 特指CH9329（无后缀）芯片。
2、CH9329F 的0#引脚是QFN 封装的底板，是必要连接。 3、优选CH9329F，性能更优，速度更快，功能更齐全。 4、本手册中当CH9329 与CH9329F 并列或先后出现时，CH9329 特指CH9329（无后缀）芯片。
P9 · p09_fig01EXACT PACKAGE
CH9329F (QFN-32(4x4)) — 7.1 QFN32 封装
7.1 QFN32 封装
P1 · p01_fig011453×604px
CH9329F (QFN-32(4x4)) — 图1-1 CH9329 应用框图 2、特点
图1-1 CH9329 应用框图 2、特点
P9 · p09_fig021103×1140px
CH9329F (QFN-32(4x4)) — V1.2 9
V1.2 9
P10 · p10_fig011808×1909px
CH9329F (QFN-32(4x4)) — CH9329 手册 https://wch.cn
CH9329 手册 https://wch.cn
P10 · p10_fig01P10
CH9329F (QFN-32(4x4)) — Datasheet Page 10 (p10_fig01)
Datasheet Page 10 (p10_fig01)

Technical Specifications & Part Details (CH9329F)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9329F (QFN-32(4x4)) is a 32-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.3V to 5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.3V to 5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-32(4x4))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (GPIO0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol33 auto-grouped pins
OK
IPC-7351B Land Pattern33 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 2.70×2.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-32(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-32(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9329F (QFN-32(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9329F (QFN-32(4x4))?

Manufactured by WCH, the CH9329F is housed in a QFN-32(4x4) package with 33 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 3.3V to 5V. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 3 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 4 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 5 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 6 (VDD33: Power Supply Input (VDD33 — 3.3V to 5V)).

What are the IPC-7351B PCB Footprint dimensions for CH9329F?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9329F (QFN-32(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.40 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 2.70 × 2.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9329F?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9329F (WCH, QFN-32(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & CH9329 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1IO1Digital_IOGeneral Purpose Digital I/O Pin IO1
2NCNCSignal terminal NC (I/O, 3.3V to 5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
3NCNCSignal terminal NC (I/O, 3.3V to 5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
4NCNCSignal terminal NC (I/O, 3.3V to 5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
5NCNCSignal terminal NC (I/O, 3.3V to 5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
6VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V to 5V domain (Max rating: 5.0V).
7UD-Digital_IOSignal terminal UD- (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB.
8UD+Digital_IOSignal terminal UD+ (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
9IO4Digital_IOGPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10DEFDigital_IOSignal terminal DEF (I/O, 3.3V to 5V domain). Multiplexed alternate functions: DEF. Supported peripheral buses: General.
11SETDigital_IOSignal terminal SET (I/O, 3.3V to 5V domain). Multiplexed alternate functions: SET. Supported peripheral buses: General.
12UD+Digital_IOSignal terminal UD+ (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
13UD -Digital_IOSignal terminal UD - (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD -. Supported peripheral buses: General.
14GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
15VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V to 5V domain (Max rating: 5.0V).
16V33Power_InPrimary positive power supply input (V33) operating in the 3.3V to 5V domain (Max rating: 5.0V).
17GPIO4Digital_IOSignal terminal GPIO4 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: GPIO4. Supported peripheral buses: General.
18TP_ENDigital_IOSignal terminal TP_EN (I/O, 3.3V to 5V domain). Multiplexed alternate functions: TP_EN. Supported peripheral buses: General.
19VIODigital_IOSignal terminal VIO (I/O, 3.3V to 5V domain). Multiplexed alternate functions: VIO. Supported peripheral buses: General.
20SETDigital_IOSignal terminal SET (I/O, 3.3V to 5V domain). Multiplexed alternate functions: SET. Supported peripheral buses: General.
21DEFDigital_IOSignal terminal DEF (I/O, 3.3V to 5V domain). Multiplexed alternate functions: DEF. Supported peripheral buses: General.
22RTS/FLC_ENDigital_IOSignal terminal RTS/FLC_EN (I/O, 3.3V to 5V domain). Multiplexed alternate functions: RTS/FLC_EN. Supported peripheral buses: UART.
23CTSDigital_IOSignal terminal CTS (I/O, 3.3V to 5V domain). Multiplexed alternate functions: CTS. Supported peripheral buses: UART.
24TNOWDigital_IOSignal terminal TNOW (I/O, 3.3V to 5V domain). Multiplexed alternate functions: TNOW. Supported peripheral buses: General.
25RXDDigital_IOSignal terminal RXD (I/O, 3.3V to 5V domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART.
26TXDDigital_IOSignal terminal TXD (I/O, 3.3V to 5V domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
27CFG0Digital_IOSignal terminal CFG0 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: CFG0. Supported peripheral buses: General.
28CFG1Digital_IOSignal terminal CFG1 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: CFG1. Supported peripheral buses: General.
29GPIO0Digital_IOSignal terminal GPIO0 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: GPIO0. Supported peripheral buses: General.
30GPIO1Digital_IOSignal terminal GPIO1 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: GPIO1. Supported peripheral buses: General.
31GPIO2Digital_IOSignal terminal GPIO2 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: GPIO2. Supported peripheral buses: General.
32GPIO3Digital_IOSignal terminal GPIO3 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: GPIO3. Supported peripheral buses: General.
33GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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