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CH555L (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH555L

WCHID: C2761355LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH555L (LQFP-48(7x7))1P1.6/MISO/RX2PL.7/SCK/TXD3P6.4/DCO4P3.0/RXD5P4.56P4.47P3.1/TXD8P3.2/INT09P3.3/INT110P3.4/T011P3.5/T1/MOSI12P3.6/MISO113P3.7/SCK114P4.315P4.216P4.617P4.718P7.0/XI19P7.1/XO/RST#20P4.121P4.022P2.023P2.124P2.248P1.5/MOSI/AI47P1.4/SCS/AIN46P1.3/AIN345P1.2/INT0_/A44P1.1/T2EX/CA43P1.0/T2/CAP142V3341GND/VSS40VDD39P0.0/SCL0/AI38P0.1/SDA0/AI37P0.2/RXD_/AI36P0.3/TXD_/AI35P0.4/AIN1234P0.5/AIN1333P0.632P0.731P6.0/DM30P6.1/DP29P2.7/TXD128P2.6/RXD127P2.5/T2EX_/C26P2.4/T2_/CAP25P2.3Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.235.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1P1.6/MISO/RXD1_/AIN6I/OMultiplexed I/O & Peripheral Pin P1.6/MISO/RXD1_/AIN6 (UART, SPI, ADC)
2PL.7/SCK/TXD1_/AIN7I/OMultiplexed I/O & Peripheral Pin PL.7/SCK/TXD1_/AIN7 (UART, SPI, ADC)
3P6.4/DCOI/OMultiplexed I/O & Peripheral Pin P6.4/DCO (General)
4P3.0/RXDI/OMultiplexed I/O & Peripheral Pin P3.0/RXD (UART)
5P4.5I/OMultiplexed I/O & Peripheral Pin P4.5 (General)
6P4.4I/OMultiplexed I/O & Peripheral Pin P4.4 (General)
7P3.1/TXDI/OMultiplexed I/O & Peripheral Pin P3.1/TXD (UART)
8P3.2/INT0I/OMultiplexed I/O & Peripheral Pin P3.2/INT0 (General)
9P3.3/INT1I/OMultiplexed I/O & Peripheral Pin P3.3/INT1 (General)
10P3.4/T0I/OMultiplexed I/O & Peripheral Pin P3.4/T0 (General)
11P3.5/T1/MOSI1I/OMultiplexed I/O & Peripheral Pin P3.5/T1/MOSI1 (SPI)
12P3.6/MISO1I/OMultiplexed I/O & Peripheral Pin P3.6/MISO1 (SPI)
13P3.7/SCK1I/OMultiplexed I/O & Peripheral Pin P3.7/SCK1 (SPI)
14P4.3I/OMultiplexed I/O & Peripheral Pin P4.3 (General)
15P4.2I/OMultiplexed I/O & Peripheral Pin P4.2 (General)
16P4.6I/OMultiplexed I/O & Peripheral Pin P4.6 (General)
17P4.7I/OMultiplexed I/O & Peripheral Pin P4.7 (General)
18P7.0/XII/OMultiplexed I/O & Peripheral Pin P7.0/XI (RTC/CLK)
19P7.1/XO/RST#/ALE_I/OMultiplexed I/O & Peripheral Pin P7.1/XO/RST#/ALE_ (RTC/CLK)
20P4.1I/OMultiplexed I/O & Peripheral Pin P4.1 (General)
21P4.0I/OMultiplexed I/O & Peripheral Pin P4.0 (General)
22P2.0I/OMultiplexed I/O & Peripheral Pin P2.0 (General)
23P2.1I/OMultiplexed I/O & Peripheral Pin P2.1 (General)
24P2.2I/OMultiplexed I/O & Peripheral Pin P2.2 (General)
25P2.3I/OMultiplexed I/O & Peripheral Pin P2.3 (General)
26P2.4/T2_/CAP1_I/OMultiplexed I/O & Peripheral Pin P2.4/T2_/CAP1_ (General)
27P2.5/T2EX_/CAP2_I/OMultiplexed I/O & Peripheral Pin P2.5/T2EX_/CAP2_ (General)
28P2.6/RXD1I/OMultiplexed I/O & Peripheral Pin P2.6/RXD1 (UART)
29P2.7/TXD1I/OMultiplexed I/O & Peripheral Pin P2.7/TXD1 (UART)
30P6.1/DPI/OMultiplexed I/O & Peripheral Pin P6.1/DP (General)
31P6.0/DMI/OMultiplexed I/O & Peripheral Pin P6.0/DM (General)
32P0.7I/OMultiplexed I/O & Peripheral Pin P0.7 (General)
33P0.6I/OMultiplexed I/O & Peripheral Pin P0.6 (General)
34P0.5/AIN13I/OMultiplexed I/O & Peripheral Pin P0.5/AIN13 (ADC)
35P0.4/AIN12I/OMultiplexed I/O & Peripheral Pin P0.4/AIN12 (ADC)
36P0.3/TXD_/AIN11I/OMultiplexed I/O & Peripheral Pin P0.3/TXD_/AIN11 (UART, ADC)
37P0.2/RXD_/AIN10I/OMultiplexed I/O & Peripheral Pin P0.2/RXD_/AIN10 (UART, ADC)
38P0.1/SDA0/AIN9I/OMultiplexed I/O & Peripheral Pin P0.1/SDA0/AIN9 (I2C, ADC)
39P0.0/SCL0/AIN8I/OMultiplexed I/O & Peripheral Pin P0.0/SCL0/AIN8 (I2C, ADC)
40VDDPowerPower Supply Input (VDD — 4.5V ~ 16.0V VCC)
41GND/VSSGNDGround Reference Pin (GND/VSS)
42V33PowerPower Supply Input (V33 — 4.5V ~ 16.0V VCC)
43P1.0/T2/CAP1/AIN0I/OMultiplexed I/O & Peripheral Pin P1.0/T2/CAP1/AIN0 (ADC)
44P1.1/T2EX/CAP2/AIN1I/OMultiplexed I/O & Peripheral Pin P1.1/T2EX/CAP2/AIN1 (ADC)
45P1.2/INT0_/AIN2I/OMultiplexed I/O & Peripheral Pin P1.2/INT0_/AIN2 (ADC)
46P1.3/AIN3I/OMultiplexed I/O & Peripheral Pin P1.3/AIN3 (ADC)
47P1.4/SCS/AIN4I/OMultiplexed I/O & Peripheral Pin P1.4/SCS/AIN4 (ADC)
48P1.5/MOSI/AIN5I/OMultiplexed I/O & Peripheral Pin P1.5/MOSI/AIN5 (SPI, ADC)
PIN 1 P1.6/MISO/RXD1_/AIN6
I/O
Multiplexed I/O & Peripheral Pin P1.6/MISO/RXD1_/AIN6 (UART, SPI, ADC)
Design note: Signal terminal P1.6/MISO/RXD1_/AIN6 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P1.6/MISO/RXD1_/AIN6. Supported peripheral buses: UART, SPI, ADC.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH555L (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH555L (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH555L (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH555L (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH555L (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH555L (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH555L (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for CH555
P1 · p01_fig011736×914px
CH555L (LQFP-48(7x7)) — 2、特点
2、特点
P2 · p02_fig01958×958px
CH555L (LQFP-48(7x7)) — P1.5/MOSI/AIN5 48 | P1.6/MISO/RXD1_/AIN6 1 | P1.7/SCK/TXD1_/AIN7 2 | P6.4/DCO 3 | P3.0/RXD 4 | P4.4 6 | P3.1/TXD 7 | P3.2/INT0 8 | P3.3/INT1 9 | P3.4/T0 10 | P4.6 16 P4.7 17 | GND/VSS 41 P4.0 21 P2.0 22 P2.1 23 P2.2 24 | P2.3 25 P2.4/T2_/CA
P1.5/MOSI/AIN5 48 | P1.6/MISO/RXD1_/AIN6 1 | P1.7/SCK/TXD1_/AIN7 2 | P6.4/DCO 3 | P3.0/RXD 4 | P4.4 6 | P3.1/TXD 7 | P3.2/INT0 8 | P3.3/INT1 9 | P3.4/T0 10 | P4.6 16 P4.7 17 | GND/VSS 41 P4.0 21 P2.0 22 P2.1 23 P2.2 24 | P2.3 25 P2.4/T2_/CA
P2 · p02_fig01P2
CH555L (LQFP-48(7x7)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P3 · p03_fig011722×1431px
CH555L (LQFP-48(7x7)) — 4、引脚
4、引脚
P20 · p20_fig011731×468px
CH555L (LQFP-48(7x7)) — CH555 手册 20 | 3.3V 或2.8V 包括小于3.6V | 输入外部3.3V 电压到I/O 及电压调整器， | 必须对地接不小于0.1uF 退耦电容 | 短接VDD 输入作为内部USB 电源， 必须对地接不小于0.1uF 退耦电容 | 5V 包括大于3.6V | 输入外部5V 电压到I/O 及电压调整器， | 必须对地接不小于0.1uF 退耦电容 | 内部电压调整器3.3V 输出 及3.3V 内部USB 电源输入， 必须对地接不小于0.1uF 退耦电容 | 在电源
CH555 手册 20 | 3.3V 或2.8V 包括小于3.6V | 输入外部3.3V 电压到I/O 及电压调整器， | 必须对地接不小于0.1uF 退耦电容 | 短接VDD 输入作为内部USB 电源， 必须对地接不小于0.1uF 退耦电容 | 5V 包括大于3.6V | 输入外部5V 电压到I/O 及电压调整器， | 必须对地接不小于0.1uF 退耦电容 | 内部电压调整器3.3V 输出 及3.3V 内部USB 电源输入， 必须对地接不小于0.1uF 退耦电容 | 在电源
P20 · p20_fig021757×2035px
CH555L (LQFP-48(7x7)) — 在电源上电或者系统复位后，CH555 默认处于运行状态。在性能满足要求的前提下，适当降低 系统主频可以降低运行时的功耗。当CH555 完全不需要运行时，可以设置PCON 中的PD 进入睡眠状 态，睡眠状态下可以选择通过USB、UART0、UART1、SPI0 以及部分GPIO 进行外部唤醒。 7.2 电源和睡眠控制寄存器 表7.2.1 电源和睡眠控制寄存器列表 | 名称 地址 描述 复位值 | WDOG_COUNT FFh 看门狗计数寄存器 00h | RESET_KEEP
在电源上电或者系统复位后，CH555 默认处于运行状态。在性能满足要求的前提下，适当降低 系统主频可以降低运行时的功耗。当CH555 完全不需要运行时，可以设置PCON 中的PD 进入睡眠状 态，睡眠状态下可以选择通过USB、UART0、UART1、SPI0 以及部分GPIO 进行外部唤醒。 7.2 电源和睡眠控制寄存器 表7.2.1 电源和睡眠控制寄存器列表 | 名称 地址 描述 复位值 | WDOG_COUNT FFh 看门狗计数寄存器 00h | RESET_KEEP
P20 · p20_fig01P20
CH555L (LQFP-48(7x7)) — Datasheet Page 20 (p20_fig01)
Datasheet Page 20 (p20_fig01)
P30 · p30_fig011757×593px
CH555L (LQFP-48(7x7)) — [7:0] Pm.0～Pm.7 RW Pm.x 引脚状态输入位 PPh
[7:0] Pm.0～Pm.7 RW Pm.x 引脚状态输入位 PPh
P30 · p30_fig021757×591px
CH555L (LQFP-48(7x7)) — 位 名称 访问 描述 复位值
位 名称 访问 描述 复位值
P47 · p47_fig011757×2171px
CH555L (LQFP-48(7x7)) — 位 名称 访问 描述 复位值
位 名称 访问 描述 复位值
P50 · p50_fig011757×1621px
CH555L (LQFP-48(7x7)) — 该CMP 的正相输入端有两种输入选择：当bCMP_PIN=1 时选择经电阻分压连接到上述ADC 模拟输 入通道；当bCMP_PIN=0 时选择经电阻分压输入VDD 电源。反相输入端由MASK_CMP_VREF 选择参考电 压，该CMP 一般主要用于电源电压监测和DC-DC 控制，参考7.2 节。 15.2 ADC 寄存器 表15.2.1 ADC 相关寄存器列表 | 名称 地址 描述 复位值 | ADC_CTRL F3h ADC 控制和状态寄存器 xxh | ADC_DAT_H
该CMP 的正相输入端有两种输入选择：当bCMP_PIN=1 时选择经电阻分压连接到上述ADC 模拟输 入通道；当bCMP_PIN=0 时选择经电阻分压输入VDD 电源。反相输入端由MASK_CMP_VREF 选择参考电 压，该CMP 一般主要用于电源电压监测和DC-DC 控制，参考7.2 节。 15.2 ADC 寄存器 表15.2.1 ADC 相关寄存器列表 | 名称 地址 描述 复位值 | ADC_CTRL F3h ADC 控制和状态寄存器 xxh | ADC_DAT_H
P66 · p66_fig011757×1883px
CH555L (LQFP-48(7x7)) — CH555 手册 66 | IUP3I I2C 引脚带上拉电阻输入端的输入电流 140 280 440 uA | Rsw3 ADC 等模块的模拟开关的导通电阻 600 1000 2500 Ω | Vpot 电源上电复位的门限电压 2.3 2.7 3.0 V | 19.4 时序参数(测试条件：TA=25℃，VDD=5V 或VDD=V33=3.3V，Fsys=12MHz) | 名称 参数说明 最小值 典型值 最大值 单位 | Fxt 外部晶体频率或者XI 输入时钟频率 6 24
CH555 手册 66 | IUP3I I2C 引脚带上拉电阻输入端的输入电流 140 280 440 uA | Rsw3 ADC 等模块的模拟开关的导通电阻 600 1000 2500 Ω | Vpot 电源上电复位的门限电压 2.3 2.7 3.0 V | 19.4 时序参数(测试条件：TA=25℃，VDD=5V 或VDD=V33=3.3V，Fsys=12MHz) | 名称 参数说明 最小值 典型值 最大值 单位 | Fxt 外部晶体频率或者XI 输入时钟频率 6 24
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (CH555L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Interface Bridge / Precision Clock & Timer IC
Detailed Overview:CH555L (LQFP-48(7x7)) is a 48-pin interface bridge / precision clock & timer ic featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
40MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C_ctrl
BOM
10nF (0.01µF) Ceramic
0603 / Disc
Keep traces as short as possible, place decoupling caps close to VCC pin.
C_dec
BOM
100nF Ceramic + 10µF Electrolytic
Radial / 0805
Supply transient bypass (~150mA shoot-through spikes) on VCC (Pin 8) — place adjacent to Pins 8-1.
R1, R2 + C_timing
BOM
R1=4.7kΩ, R2=47kΩ, C=100nF
0603 / THT
RC timing network on DISCH (Pin 7), THRES (Pin 6), TRIG (Pin 2) — tie RESET (Pin 4) to VCC if unused.
SA555P / SE555P
Texas Instruments
100% Drop-in100% Pin-to-Pin DIP-8 equivalent for 555 timer designs.
TLC555CP / LMC555CN
Texas Instruments
100% Drop-in100% Pin-to-Pin DIP-8 equivalent for 555 timer designs.

Technical Frequently Asked Questions (FAQ) — CH555L (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH555L (LQFP-48(7x7))?

Manufactured by WCH, the CH555L is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (P1.6/MISO/RXD1_/AIN6: Multiplexed I/O & Peripheral Pin P1.6/MISO/RXD1_/AIN6 (UART, SPI, ADC)), 2 (PL.7/SCK/TXD1_/AIN7: Multiplexed I/O & Peripheral Pin PL.7/SCK/TXD1_/AIN7 (UART, SPI, ADC)), 3 (P6.4/DCO: Multiplexed I/O & Peripheral Pin P6.4/DCO (General)), 4 (P3.0/RXD: Multiplexed I/O & Peripheral Pin P3.0/RXD (UART)), 5 (P4.5: Multiplexed I/O & Peripheral Pin P4.5 (General)), 6 (P4.4: Multiplexed I/O & Peripheral Pin P4.4 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH555L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH555L (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH555L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH555L (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH555 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1P1.6/MISO/RXD1_/AIN6Digital_IOSignal terminal P1.6/MISO/RXD1_/AIN6 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P1.6/MISO/RXD1_/AIN6. Supported peripheral buses: UART, SPI, ADC.
2PL.7/SCK/TXD1_/AIN7Digital_IOSignal terminal PL.7/SCK/TXD1_/AIN7 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: PL.7/SCK/TXD1_/AIN7. Supported peripheral buses: UART, SPI, ADC.
3P6.4/DCODigital_IOSignal terminal P6.4/DCO (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P6.4/DCO. Supported peripheral buses: General.
4P3.0/RXDDigital_IOSignal terminal P3.0/RXD (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P3.0/RXD. Supported peripheral buses: UART.
5P4.5Digital_IOSignal terminal P4.5 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P4.5. Supported peripheral buses: General.
6P4.4Digital_IOSignal terminal P4.4 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P4.4. Supported peripheral buses: General.
7P3.1/TXDDigital_IOSignal terminal P3.1/TXD (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P3.1/TXD. Supported peripheral buses: UART.
8P3.2/INT0Digital_IOSignal terminal P3.2/INT0 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P3.2/INT0. Supported peripheral buses: General.
9P3.3/INT1Digital_IOSignal terminal P3.3/INT1 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P3.3/INT1. Supported peripheral buses: General.
10P3.4/T0Digital_IOSignal terminal P3.4/T0 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P3.4/T0. Supported peripheral buses: General.
11P3.5/T1/MOSI1Digital_IOSignal terminal P3.5/T1/MOSI1 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P3.5/T1/MOSI1. Supported peripheral buses: SPI.
12P3.6/MISO1Digital_IOSignal terminal P3.6/MISO1 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P3.6/MISO1. Supported peripheral buses: SPI.
13P3.7/SCK1Digital_IOSignal terminal P3.7/SCK1 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P3.7/SCK1. Supported peripheral buses: SPI.
14P4.3Digital_IOSignal terminal P4.3 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P4.3. Supported peripheral buses: General.
15P4.2Digital_IOSignal terminal P4.2 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P4.2. Supported peripheral buses: General.
16P4.6Digital_IOSignal terminal P4.6 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P4.6. Supported peripheral buses: General.
17P4.7Digital_IOSignal terminal P4.7 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P4.7. Supported peripheral buses: General.
18P7.0/XIDigital_IOSignal terminal P7.0/XI (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P7.0/XI. Supported peripheral buses: RTC/CLK.
19P7.1/XO/RST#/ALE_Digital_IOSignal terminal P7.1/XO/RST#/ALE_ (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P7.1/XO/RST#/ALE_. Supported peripheral buses: RTC/CLK.
20P4.1Digital_IOSignal terminal P4.1 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P4.1. Supported peripheral buses: General.
21P4.0Digital_IOSignal terminal P4.0 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P4.0. Supported peripheral buses: General.
22P2.0Digital_IOSignal terminal P2.0 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P2.0. Supported peripheral buses: General.
23P2.1Digital_IOSignal terminal P2.1 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P2.1. Supported peripheral buses: General.
24P2.2Digital_IOSignal terminal P2.2 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P2.2. Supported peripheral buses: General.
25P2.3Digital_IOSignal terminal P2.3 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P2.3. Supported peripheral buses: General.
26P2.4/T2_/CAP1_Digital_IOSignal terminal P2.4/T2_/CAP1_ (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P2.4/T2_/CAP1_. Supported peripheral buses: General.
27P2.5/T2EX_/CAP2_Digital_IOSignal terminal P2.5/T2EX_/CAP2_ (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P2.5/T2EX_/CAP2_. Supported peripheral buses: General.
28P2.6/RXD1Digital_IOSignal terminal P2.6/RXD1 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P2.6/RXD1. Supported peripheral buses: UART.
29P2.7/TXD1Digital_IOSignal terminal P2.7/TXD1 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P2.7/TXD1. Supported peripheral buses: UART.
30P6.1/DPDigital_IOSignal terminal P6.1/DP (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P6.1/DP. Supported peripheral buses: General.
31P6.0/DMDigital_IOSignal terminal P6.0/DM (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P6.0/DM. Supported peripheral buses: General.
32P0.7Digital_IOSignal terminal P0.7 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P0.7. Supported peripheral buses: General.
33P0.6Digital_IOSignal terminal P0.6 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P0.6. Supported peripheral buses: General.
34P0.5/AIN13AnalogSignal terminal P0.5/AIN13 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P0.5/AIN13. Supported peripheral buses: ADC.
35P0.4/AIN12AnalogSignal terminal P0.4/AIN12 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P0.4/AIN12. Supported peripheral buses: ADC.
36P0.3/TXD_/AIN11Digital_IOSignal terminal P0.3/TXD_/AIN11 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P0.3/TXD_/AIN11. Supported peripheral buses: UART, ADC.
37P0.2/RXD_/AIN10Digital_IOSignal terminal P0.2/RXD_/AIN10 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P0.2/RXD_/AIN10. Supported peripheral buses: UART, ADC.
38P0.1/SDA0/AIN9Digital_IOSignal terminal P0.1/SDA0/AIN9 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P0.1/SDA0/AIN9. Supported peripheral buses: I2C, ADC.
39P0.0/SCL0/AIN8Digital_IOSignal terminal P0.0/SCL0/AIN8 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P0.0/SCL0/AIN8. Supported peripheral buses: I2C, ADC.
40VDDPower_InPrimary positive power supply input (VDD) operating in the 4.5V ~ 16.0V VCC domain (Max rating: 18.0V).
41GND/VSSGND0V electrical ground return terminal (GND/VSS) for internal core logic, I/O drivers, and analog sub-blocks.
42V33Power_InPrimary positive power supply input (V33) operating in the 4.5V ~ 16.0V VCC domain (Max rating: 18.0V).
43P1.0/T2/CAP1/AIN0AnalogSignal terminal P1.0/T2/CAP1/AIN0 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P1.0/T2/CAP1/AIN0. Supported peripheral buses: ADC.
44P1.1/T2EX/CAP2/AIN1AnalogSignal terminal P1.1/T2EX/CAP2/AIN1 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P1.1/T2EX/CAP2/AIN1. Supported peripheral buses: ADC.
45P1.2/INT0_/AIN2AnalogSignal terminal P1.2/INT0_/AIN2 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P1.2/INT0_/AIN2. Supported peripheral buses: ADC.
46P1.3/AIN3AnalogSignal terminal P1.3/AIN3 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P1.3/AIN3. Supported peripheral buses: ADC.
47P1.4/SCS/AIN4AnalogSignal terminal P1.4/SCS/AIN4 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P1.4/SCS/AIN4. Supported peripheral buses: ADC.
48P1.5/MOSI/AIN5Digital_IOSignal terminal P1.5/MOSI/AIN5 (I/O, 4.5V ~ 16.0V VCC domain). Multiplexed alternate functions: P1.5/MOSI/AIN5. Supported peripheral buses: SPI, ADC.
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