WLCSP-39 · 39P
Synchronized Pinout (Symbol / 2D / 3D) (39/39)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| A1 | PA14 | I/O | Multiplexed I/O & Peripheral Pin PA14 (General) |
| A3 | PA15 | I/O | Multiplexed I/O & Peripheral Pin PA15 (General) |
| A5 | PB3 | I/O | Multiplexed I/O & Peripheral Pin PB3 (General) |
| A7 | PB4 | I/O | Multiplexed I/O & Peripheral Pin PB4 (General) |
| A9 | VCAP | I/O | Multiplexed I/O & Peripheral Pin VCAP (General) |
| A11 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| B2 | PA12 | I/O | Multiplexed I/O & Peripheral Pin PA12 (General) |
| B4 | PA13 | I/O | Multiplexed I/O & Peripheral Pin PA13 (General) |
| B6 | BOOT0 | I | Input-Only Pin BOOT0 (General) |
| B8 | VBAT | Power | Power Supply Input (VBAT — 3.3V VDD (Max 4.0V)) |
| B10 | VSS | GND | Ground Reference Pin (VSS) |
| C1 | PA11 | I/O | Multiplexed I/O & Peripheral Pin PA11 (General) |
| C3 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (General) |
| C5 | PB8 | I/O | Multiplexed I/O & Peripheral Pin PB8 (General) |
| C7 | PC13 | I/O | Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK) |
| C9 | PC15 - OSC32_OUT | I/O | Multiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK) |
| C11 | IOC11 | I/O | General Purpose Digital I/O Pin IOC11 |
| D2 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (General) |
| D4 | PA3 | I/O | Multiplexed I/O & Peripheral Pin PA3 (SPI, ADC, PWM) |
| D6 | PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM) |
| D8 | PH1OSC OUT -_ (PH1) | I/O | Multiplexed I/O & Peripheral Pin PH1OSC OUT -_ (PH1) (RTC/CLK) |
| D10 | PH0OSC IN -_ (PH0) | I/O | Multiplexed I/O & Peripheral Pin PH0OSC IN -_ (PH0) (RTC/CLK) |
| E1 | PB15 | I/O | Multiplexed I/O & Peripheral Pin PB15 (UART, SPI, PWM, RTC/CLK) |
| E3 | PA5 | I/O | Multiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM) |
| E5 | PA4 | I/O | Multiplexed I/O & Peripheral Pin PA4 (SPI, ADC) |
| E7 | PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 (ADC, PWM) |
| E9 | PA0 | I/O | Multiplexed I/O & Peripheral Pin PA0 (UART, SPI, ADC, PWM) |
| E11 | NRST | I | System Enable & Hardware Reset (NRST) |
| F2 | VSS | GND | Ground Reference Pin (VSS) |
| F4 | PA6 | I/O | Multiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM) |
| F6 | PA7 | I/O | Multiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM) |
| F8 | VSS | GND | Ground Reference Pin (VSS) |
| F10 | VSSA | GND | Ground Reference Pin (VSSA) |
| G1 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| G3 | VCAP | I/O | Multiplexed I/O & Peripheral Pin VCAP (General) |
| G5 | PB1 | I/O | Multiplexed I/O & Peripheral Pin PB1 (SPI, ADC, PWM) |
| G7 | PB0 | I/O | Multiplexed I/O & Peripheral Pin PB0 (UART, SPI, ADC, PWM) |
| G9 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| G11 | VDDA | Power | Power Supply Input (VDDA — 3.3V VDD (Max 4.0V)) |
PIN A1 PA14
I/OMultiplexed I/O & Peripheral Pin PA14 (General)
Design note: Signal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 23 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (39 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
WLCSP-39 · 2.80×2.80mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (39 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (23 figures · Page 1/2)
Showing 1–12 of 23 uncropped original figures for STM32H523
P58 · p58_fig01EXACT PACKAGE
P197 · p197_fig01EXACT PACKAGE
P1 · p01_fig011751×1042px
P58 · p58_fig021546×1193px
P59 · p59_fig011546×988px
P59 · p59_fig021546×1287px
P60 · p60_fig011549×1326px
P60 · p60_fig021546×1296px
P94 · p94_fig011752×2012px
P94 · p94_fig01P94
P117 · p117_fig011546×519px
P118 · p118_fig011546×521px
Page 1 / 2 (23 extracted figures)
Technical Specifications & Part Details (STM32H523HEY6TR)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:STM32H523HEY6TR (WLCSP-39) is a 39-pin embedded microcontroller unit (mcu) featuring a 2.80 × 2.80 × 0.48 mm mechanical envelope (lead pitch e = 0.39 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
250 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
14 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
2.80 × 2.80 × 0.48 mm (A1=0.18 mm)
Package family: WLCSP (WLCSP-39)
Pin Count & Lead PitchN / e
39 Pins | Pitch e = 0.39 mm (15.4 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol39 auto-grouped pins
IPC-7351B Land Pattern39 pads · Pitch 0.40mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — STM32H523 (5)
LQFP-48(7x7) · 48P
LQFP-64(10x10) · 64P
IPC-7351B
64P10.0×10.0×1.60mmP=0.5mm
STM32H523 (LQFP-64(10x10))
LQFP-100(14x14) · 100P
IPC-7351B
100P14.0×14.0×1.55mmP=0.5mm
STM32H523 (LQFP-100(14x14))
UFBGA-100(7x7) · 100P
Mechanical Dimensions & Land Pattern (WLCSP-39)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
2.80 × 2.80 mm
Height (A) & Pitch (e)IPC-7351B
A=0.48mm · e=0.40mm
Pad Size (W × L)Level B
0.21 × 0.21 mm
Pins / Total PadsTopology
39P / 39Pad (BGA_GRID)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit WLCSP-39 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32H523HEY6TR (WLCSP-39)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32H523HEY6TR (WLCSP-39)?
Manufactured by ST, the STM32H523HEY6TR is housed in a WLCSP-39 package with 39 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (PA14: Multiplexed I/O & Peripheral Pin PA14 (General)), A3 (PA15: Multiplexed I/O & Peripheral Pin PA15 (General)), A5 (PB3: Multiplexed I/O & Peripheral Pin PB3 (General)), A7 (PB4: Multiplexed I/O & Peripheral Pin PB4 (General)), A9 (VCAP: Multiplexed I/O & Peripheral Pin VCAP (General)), A11 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))).
What are the IPC-7351B PCB Footprint dimensions for STM32H523HEY6TR?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H523HEY6TR (WLCSP-39) has a nominal body envelope of 2.80 × 2.80 mm, pitch e = 0.40 mm, and 39 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H523HEY6TR?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H523HEY6TR (ST, WLCSP-39) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (39 pins) & STM32H523 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| A1 | PA14 | Digital_IO | Signal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General. |
| A3 | PA15 | Digital_IO | Signal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General. |
| A5 | PB3 | Digital_IO | Signal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General. |
| A7 | PB4 | Digital_IO | Signal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General. |
| A9 | VCAP | Digital_IO | Signal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General. |
| A11 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| B2 | PA12 | Digital_IO | Signal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General. |
| B4 | PA13 | Digital_IO | Signal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General. |
| B6 | BOOT0 | Digital_IO | Signal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General. |
| B8 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| B10 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| C1 | PA11 | Digital_IO | Signal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General. |
| C3 | PB7 | Digital_IO | Signal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General. |
| C5 | PB8 | Digital_IO | Signal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General. |
| C7 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK. |
| C9 | PC15 - OSC32_OUT | Digital_IO | Signal terminal PC15 - OSC32_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15 - OSC32_OUT. Supported peripheral buses: RTC/CLK. |
| C11 | IOC11 | Digital_IO | General Purpose Digital I/O Pin IOC11 |
| D2 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General. |
| D4 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS, SPI3_MOSI. Supported peripheral buses: SPI, ADC, PWM. |
| D6 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM. |
| D8 | PH1OSC OUT -_ (PH1) | Digital_IO | Signal terminal PH1OSC OUT -_ (PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1OSC OUT -_ (PH1). Supported peripheral buses: RTC/CLK. |
| D10 | PH0OSC IN -_ (PH0) | Digital_IO | Signal terminal PH0OSC IN -_ (PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0OSC IN -_ (PH0). Supported peripheral buses: RTC/CLK. |
| E1 | PB15 | Digital_IO | Signal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI, SPI1_MOSI. Supported peripheral buses: UART, SPI, PWM, RTC/CLK. |
| E3 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, DAC, PWM. |
| E5 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_MOSI, SPI1_NSS, SPI3_NSS. Supported peripheral buses: SPI, ADC. |
| E7 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: ADC, PWM. |
| E9 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_SCKSPI3RDY. Supported peripheral buses: UART, SPI, ADC, PWM. |
| E11 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| F2 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| F4 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC, PWM. |
| F6 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM. |
| F8 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| F10 | VSSA | GND | 0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks. |
| G1 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| G3 | VCAP | Digital_IO | Signal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General. |
| G5 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK, SPI2_NSS. Supported peripheral buses: SPI, ADC, PWM. |
| G7 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI, ADC, PWM. |
| G9 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| G11 | VDDA | Power_In | Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |