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KP18106WPA (HSOP-8-EP-4.1mm) — Symbol, Footprint IPC-7351B & 3D STEP Model

KP18106WPA

Kiwi InstrumentsID: C2692496HSOP-8-EP-4.1mm · 9 Pins · Pitch 0.95mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · KP18106WPA (HSOP-8-EP-4.1mm)1N2VT3RSL4RCS5LED9EP8L7HV6CoutGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.812.77.62.5-2.5-7.6-12.7mm
2. 2D FOOTPRINT
123458769E=6.40mm · Pitch e=0.95mmD=4.10mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 6.40mm × 4.10mm · Pitch: 0.95mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (9/9)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1NI/OMultiplexed I/O & Peripheral Pin N (General)
2VTI/OMultiplexed I/O & Peripheral Pin VT (General)
3RSLI/OMultiplexed I/O & Peripheral Pin RSL (General)
4RCSI/OMultiplexed I/O & Peripheral Pin RCS (General)
5LEDI/OMultiplexed I/O & Peripheral Pin LED (General)
6CoutI/OMultiplexed I/O & Peripheral Pin Cout (General)
7HVI/OMultiplexed I/O & Peripheral Pin HV (General)
8LI/OMultiplexed I/O & Peripheral Pin L (General)
9EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 N
I/O
Multiplexed I/O & Peripheral Pin N (General)
Design note: Signal terminal N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: N. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: KP18106WPA (Kiwi Instruments · HSOP-8-EP-4.1mm)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
KP18106WPA (HSOP-8-EP-4.1mm) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
KP18106WPA (HSOP-8-EP-4.1mm) - 2. Standard Pinout (Top View)
True package pinout (9 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
KP18106WPA (HSOP-8-EP-4.1mm) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
KP18106WPA (HSOP-8-EP-4.1mm) - 4. Package Dimensions (D×E×A)
HSOP-8-EP-4.1mm · 6.40×4.10mm · Pitch 0.95mmExpand ›
5. Recommended Land PatternLAND PATTERN
KP18106WPA (HSOP-8-EP-4.1mm) - 5. Recommended Land Pattern
IPC-7351B Footprint (9 Pads)Expand ›
6. Application SchematicSCHEMATIC
KP18106WPA (HSOP-8-EP-4.1mm) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for KP18106
P1 · p01_fig01EXACT PACKAGE
KP18106WPA (HSOP-8-EP-4.1mm) — 高 PF 无频闪 LED 线性恒流驱动
高 PF 无频闪 LED 线性恒流驱动
P2 · p02_fig01EXACT PACKAGE
KP18106WPA (HSOP-8-EP-4.1mm) — www.kiwiinst.com 2 DS_KP18106WPA_REV1.0_CN ©Kiwi Instruments Corp. Confidential
www.kiwiinst.com 2 DS_KP18106WPA_REV1.0_CN ©Kiwi Instruments Corp. Confidential
P2 · p02_fig03EXACT PACKAGE
KP18106WPA (HSOP-8-EP-4.1mm) — XXXXXX：晶圆批次 Y：年份代码 WW：周代码，01-52 ZZ：流水码，01-99 或 A0-ZZ
XXXXXX：晶圆批次 Y：年份代码 WW：周代码，01-52 ZZ：流水码，01-99 或 A0-ZZ
P5 · p05_fig01EXACT PACKAGE
KP18106WPA (HSOP-8-EP-4.1mm) — KP18106WPA 高 PF 无频闪 LED 线性恒流驱动 | 封装尺寸 | HSOP-8 | D e5 | e4 | e1 | e2 | e2 | e2 | e3 | E | HE | ALL ROUND | a | L L1 | C | A | d3 d2 d1 | 背面 bottom view | d4 d5 | d3 | 1.67mm | 3.94mm | f2 f3 | f1 | f4 | e4
KP18106WPA 高 PF 无频闪 LED 线性恒流驱动 | 封装尺寸 | HSOP-8 | D e5 | e4 | e1 | e2 | e2 | e2 | e3 | E | HE | ALL ROUND | a | L L1 | C | A | d3 d2 d1 | 背面 bottom view | d4 d5 | d3 | 1.67mm | 3.94mm | f2 f3 | f1 | f4 | e4
P1 · p01_fig01P1
KP18106WPA (HSOP-8-EP-4.1mm) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P2 · p02_fig02376×376px
KP18106WPA (HSOP-8-EP-4.1mm) — 管脚封装
管脚封装
P2 · p02_fig03P2
KP18106WPA (HSOP-8-EP-4.1mm) — Datasheet Page 2 (p02_fig03)
Datasheet Page 2 (p02_fig03)
P3 · p03_fig011839×2466px
KP18106WPA (HSOP-8-EP-4.1mm) — 备注 4：电气工作参数定义了器件在工作范围内并且在保证特定性能指标的测试条件下的直流和交流电参数。对于未给定
备注 4：电气工作参数定义了器件在工作范围内并且在保证特定性能指标的测试条件下的直流和交流电参数。对于未给定

Technical Specifications & Part Details (KP18106WPA)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:KP18106WPA (HSOP-8-EP-4.1mm) is a 8-pin standard electronic & interconnect component featuring a 4.90 × 3.90 × 1.70 mm mechanical envelope (lead pitch e = 0.95 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.90 × 3.90 × 1.70 mm (A1=0.06 mm)
Package family: SOP (HSOP-8-EP-4.1mm)
Pin Count & Lead PitchN / e
8 Pins | Pitch e = 0.95 mm (37.4 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol9 auto-grouped pins
OK
IPC-7351B Land Pattern9 pads · Pitch 0.95mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (HSOP-8-EP-4.1mm)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.40 × 4.10 mm
Height (A) & Pitch (e)IPC-7351B
A=1.70mm · e=0.95mm
Pad Size (W × L)Level B
0.70 × 1.50 mm
Pins / Total PadsTopology
9P / 9Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
HSOP-8-EP-4.1mm
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — KP18106WPA (HSOP-8-EP-4.1mm)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of KP18106WPA (HSOP-8-EP-4.1mm)?

Manufactured by Kiwi Instruments, the KP18106WPA is housed in a HSOP-8-EP-4.1mm package with 9 pins and a 0.95 mm lead pitch. Key pins include: 1 (N: Multiplexed I/O & Peripheral Pin N (General)), 2 (VT: Multiplexed I/O & Peripheral Pin VT (General)), 3 (RSL: Multiplexed I/O & Peripheral Pin RSL (General)), 4 (RCS: Multiplexed I/O & Peripheral Pin RCS (General)), 5 (LED: Multiplexed I/O & Peripheral Pin LED (General)), 6 (Cout: Multiplexed I/O & Peripheral Pin Cout (General)).

What are the IPC-7351B PCB Footprint dimensions for KP18106WPA?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), KP18106WPA (HSOP-8-EP-4.1mm) has a nominal body envelope of 4.10 × 6.40 mm, pitch e = 0.95 mm, and 9 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for KP18106WPA?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for KP18106WPA (Kiwi Instruments, HSOP-8-EP-4.1mm) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (9 pins) & KP18106 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1NDigital_IOSignal terminal N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: N. Supported peripheral buses: General.
2VTDigital_IOSignal terminal VT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VT. Supported peripheral buses: General.
3RSLDigital_IOSignal terminal RSL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSL. Supported peripheral buses: General.
4RCSDigital_IOSignal terminal RCS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RCS. Supported peripheral buses: General.
5LEDDigital_IOSignal terminal LED (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED. Supported peripheral buses: General.
6CoutDigital_IOSignal terminal Cout (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Cout. Supported peripheral buses: General.
7HVDigital_IOSignal terminal HV (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV. Supported peripheral buses: General.
8LDigital_IOSignal terminal L (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: L. Supported peripheral buses: General.
9EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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