Mechanical Dimensions & Land Pattern (HSOP-7-EP-150mil)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit HSOP-7-EP-150mil | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — KP18001WPA (HSOP-7-EP-150mil)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of KP18001WPA (HSOP-7-EP-150mil)?
Manufactured by Kiwi Instruments, the KP18001WPA is housed in a HSOP-7-EP-150mil package with 8 pins and a 1.33 mm lead pitch. Key pins include: 1 (ACIN: Multiplexed I/O & Peripheral Pin ACIN (General)), 2 (GND: Ground Reference Pin (GND)), 3 (VT: Multiplexed I/O & Peripheral Pin VT (General)), 4 (REXT: Multiplexed I/O & Peripheral Pin REXT (General)), 5 (OUT: Multiplexed I/O & Peripheral Pin OUT (General)), 6 (HV: Multiplexed I/O & Peripheral Pin HV (General)).
What are the IPC-7351B PCB Footprint dimensions for KP18001WPA?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), KP18001WPA (HSOP-7-EP-150mil) has a nominal body envelope of 3.90 × 6.20 mm, pitch e = 1.33 mm, and 8 copper pads plus a central exposed thermal pad (EPAD) of 3.30 × 2.20 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for KP18001WPA?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for KP18001WPA (Kiwi Instruments, HSOP-7-EP-150mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (8 pins) & KP18001 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | ACIN | Digital_IO | Signal terminal ACIN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ACIN. Supported peripheral buses: General. |
| 2 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 3 | VT | Digital_IO | Signal terminal VT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VT. Supported peripheral buses: General. |
| 4 | REXT | Digital_IO | Signal terminal REXT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: REXT. Supported peripheral buses: General. |
| 5 | OUT | Digital_IO | Signal terminal OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OUT. Supported peripheral buses: General. |
| 6 | HV | Digital_IO | Signal terminal HV (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV. Supported peripheral buses: General. |
| 7 | ACIN | Digital_IO | Signal terminal ACIN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ACIN. Supported peripheral buses: General. |
| 8 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |