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CH382L (LQFP-64(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH382L

WCHID: C2685237LQFP-64(7x7) · 64 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH382L (LQFP-64(7x7))1PERST#2VCC333GND4VCC185PECKP6PECKN7VCC18A8GND9GND10RREF11PERP12PERN13VCC18A14PETN15PETP16GND17XO18XI19VCC3320SCL21SDA22ACK23BUSY24ERR25PE26SELT27RXD028DCD029RI030DSR031CTS032VCC1864CKSEL63MDSEL62MDPRT#61GND60INIT59SIN58AFD57STB56PECKP/PECKN55DTR154RTS153TXD152DTR051RTS050TXD049VCC3348GND47VCC1846D045D144D243D342D441D540D639D738CTS137DSR136RI135DCD134RXD133GNDGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.245.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364E=7.00mm · Pitch e=0.40mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PERST#I/OMultiplexed I/O & Peripheral Pin PERST# (General)
2VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
3GNDGNDGround Reference Pin (GND)
4VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
5PECKPI/OMultiplexed I/O & Peripheral Pin PECKP (General)
6PECKNI/OMultiplexed I/O & Peripheral Pin PECKN (General)
7VCC18APowerPower Supply Input (VCC18A — 3.3V / 5.0V Standard Logic)
8GNDGNDGround Reference Pin (GND)
9GNDGNDGround Reference Pin (GND)
10RREFI/OMultiplexed I/O & Peripheral Pin RREF (General)
11PERPI/OMultiplexed I/O & Peripheral Pin PERP (General)
12PERNI/OMultiplexed I/O & Peripheral Pin PERN (General)
13VCC18APowerPower Supply Input (VCC18A — 3.3V / 5.0V Standard Logic)
14PETNI/OMultiplexed I/O & Peripheral Pin PETN (General)
15PETPI/OMultiplexed I/O & Peripheral Pin PETP (General)
16GNDGNDGround Reference Pin (GND)
17XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
18XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
19VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
20SCLI/OMultiplexed I/O & Peripheral Pin SCL (I2C)
21SDAI/OMultiplexed I/O & Peripheral Pin SDA (I2C)
22ACKI/OMultiplexed I/O & Peripheral Pin ACK (General)
23BUSYI/OMultiplexed I/O & Peripheral Pin BUSY (General)
24ERRI/OMultiplexed I/O & Peripheral Pin ERR (General)
25PEI/OMultiplexed I/O & Peripheral Pin PE (General)
26SELTI/OMultiplexed I/O & Peripheral Pin SELT (General)
27RXD0I/OMultiplexed I/O & Peripheral Pin RXD0 (UART)
28DCD0I/OMultiplexed I/O & Peripheral Pin DCD0 (General)
29RI0I/OMultiplexed I/O & Peripheral Pin RI0 (General)
30DSR0I/OMultiplexed I/O & Peripheral Pin DSR0 (UART)
31CTS0I/OMultiplexed I/O & Peripheral Pin CTS0 (UART)
32VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
33GNDGNDGround Reference Pin (GND)
34RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
35DCD1I/OMultiplexed I/O & Peripheral Pin DCD1 (General)
36RI1I/OMultiplexed I/O & Peripheral Pin RI1 (General)
37DSR1I/OMultiplexed I/O & Peripheral Pin DSR1 (UART)
38CTS1I/OMultiplexed I/O & Peripheral Pin CTS1 (UART)
39D7I/OMultiplexed I/O & Peripheral Pin D7 (General)
40D6I/OMultiplexed I/O & Peripheral Pin D6 (General)
41D5I/OMultiplexed I/O & Peripheral Pin D5 (General)
42D4I/OMultiplexed I/O & Peripheral Pin D4 (General)
43D3I/OMultiplexed I/O & Peripheral Pin D3 (General)
44D2I/OMultiplexed I/O & Peripheral Pin D2 (General)
45D1I/OMultiplexed I/O & Peripheral Pin D1 (General)
46D0I/OMultiplexed I/O & Peripheral Pin D0 (General)
47VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
48GNDGNDGround Reference Pin (GND)
49VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
50TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
51RTS0I/OMultiplexed I/O & Peripheral Pin RTS0 (UART)
52DTR0I/OMultiplexed I/O & Peripheral Pin DTR0 (UART)
53TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
54RTS1I/OMultiplexed I/O & Peripheral Pin RTS1 (UART)
55DTR1I/OMultiplexed I/O & Peripheral Pin DTR1 (UART)
56PECKP/PECKNI/OMultiplexed I/O & Peripheral Pin PECKP/PECKN (General)
57STBI/OMultiplexed I/O & Peripheral Pin STB (General)
58AFDI/OMultiplexed I/O & Peripheral Pin AFD (General)
59SINI/OMultiplexed I/O & Peripheral Pin SIN (General)
60INITI/OMultiplexed I/O & Peripheral Pin INIT (General)
61GNDGNDGround Reference Pin (GND)
62MDPRT#I/OMultiplexed I/O & Peripheral Pin MDPRT# (General)
63MDSELI/OMultiplexed I/O & Peripheral Pin MDSEL (General)
64CKSELI/OMultiplexed I/O & Peripheral Pin CKSEL (General)
PIN 1 PERST#
I/O
Multiplexed I/O & Peripheral Pin PERST# (General)
Design note: Signal terminal PERST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PERST#. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH382L (WCH · LQFP-64(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH382L (LQFP-64(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH382L (LQFP-64(7x7)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH382L (LQFP-64(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH382L (LQFP-64(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-64(7x7) · 7.00×7.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH382L (LQFP-64(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH382L (LQFP-64(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for CH382
P2 · p02_fig02EXACT PACKAGE
CH382L (LQFP-64(7x7)) — Package Width of Plastic Pitch of Pin Instruction of | Package | Ordering Information | LQFP-64 7mm x 7mm 0.4mm 15.7mil Ultra small LQFP64 | patch CH382L | 4. Pins | 4.1. Power Line | Pin No. Pin Name Type Pin Description | 2,19,49 VCC33 Po
Package Width of Plastic Pitch of Pin Instruction of | Package | Ordering Information | LQFP-64 7mm x 7mm 0.4mm 15.7mil Ultra small LQFP64 | patch CH382L | 4. Pins | 4.1. Power Line | Pin No. Pin Name Type Pin Description | 2,19,49 VCC33 Po
P1 · p01_fig011647×1003px
CH382L (LQFP-64(7x7)) — dual serial ports and parallel port/printer port of PCIE bus. l Provides two-wire serial host interface, and EEPROM device similar to 24C0X which can be
dual serial ports and parallel port/printer port of PCIE bus. l Provides two-wire serial host interface, and EEPROM device similar to 24C0X which can be
P2 · p02_fig01797×797px
CH382L (LQFP-64(7x7)) — Package Width of Plastic Pitch of Pin Instruction of
Package Width of Plastic Pitch of Pin Instruction of
P3 · p03_fig011737×416px
CH382L (LQFP-64(7x7)) — Pin No. Pin Name Type Pin Description
Pin No. Pin Name Type Pin Description
P4 · p04_fig011732×449px
CH382L (LQFP-64(7x7)) — Pin No. Pin Name Type Pin Description
Pin No. Pin Name Type Pin Description

Technical Specifications & Part Details (CH382L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH382L (LQFP-64(7x7)) is a 64-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, I2C, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-64(7x7))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, I2C, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-64(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.40mm
Pad Size (W × L)Level B
0.24 × 1.25 mm
Pins / Total PadsTopology
64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-64(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH382L (LQFP-64(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH382L (LQFP-64(7x7))?

Manufactured by WCH, the CH382L is housed in a LQFP-64(7x7) package with 64 pins and a 0.40 mm lead pitch. Key pins include: 1 (PERST#: Multiplexed I/O & Peripheral Pin PERST# (General)), 2 (VCC33: Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)), 3 (GND: Ground Reference Pin (GND)), 4 (VCC18: Power Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)), 5 (PECKP: Multiplexed I/O & Peripheral Pin PECKP (General)), 6 (PECKN: Multiplexed I/O & Peripheral Pin PECKN (General)).

What are the IPC-7351B PCB Footprint dimensions for CH382L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH382L (LQFP-64(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.40 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH382L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH382L (WCH, LQFP-64(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & CH382 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PERST#Digital_IOSignal terminal PERST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PERST#. Supported peripheral buses: General.
2VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
4VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
5PECKPDigital_IOSignal terminal PECKP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PECKP. Supported peripheral buses: General.
6PECKNDigital_IOSignal terminal PECKN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PECKN. Supported peripheral buses: General.
7VCC18APower_InPrimary positive power supply input (VCC18A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
8GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
9GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
10RREFDigital_IOSignal terminal RREF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RREF. Supported peripheral buses: General.
11PERPDigital_IOSignal terminal PERP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PERP. Supported peripheral buses: General.
12PERNDigital_IOSignal terminal PERN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PERN. Supported peripheral buses: General.
13VCC18APower_InPrimary positive power supply input (VCC18A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
14PETNDigital_IOSignal terminal PETN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PETN. Supported peripheral buses: General.
15PETPDigital_IOSignal terminal PETP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PETP. Supported peripheral buses: General.
16GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
17XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
18XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
19VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
20SCLDigital_IOSignal terminal SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
21SDADigital_IOSignal terminal SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
22ACKDigital_IOSignal terminal ACK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ACK. Supported peripheral buses: General.
23BUSYDigital_IOSignal terminal BUSY (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BUSY. Supported peripheral buses: General.
24ERRDigital_IOSignal terminal ERR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ERR. Supported peripheral buses: General.
25PEDigital_IOSignal terminal PE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE. Supported peripheral buses: General.
26SELTDigital_IOSignal terminal SELT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SELT. Supported peripheral buses: General.
27RXD0Digital_IOSignal terminal RXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD0. Supported peripheral buses: UART.
28DCD0Digital_IOSignal terminal DCD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD0. Supported peripheral buses: General.
29RI0Digital_IOSignal terminal RI0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI0. Supported peripheral buses: General.
30DSR0Digital_IOSignal terminal DSR0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR0. Supported peripheral buses: UART.
31CTS0Digital_IOSignal terminal CTS0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS0. Supported peripheral buses: UART.
32VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
33GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
34RXD1Digital_IOSignal terminal RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART.
35DCD1Digital_IOSignal terminal DCD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD1. Supported peripheral buses: General.
36RI1Digital_IOSignal terminal RI1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI1. Supported peripheral buses: General.
37DSR1Digital_IOSignal terminal DSR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR1. Supported peripheral buses: UART.
38CTS1Digital_IOSignal terminal CTS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS1. Supported peripheral buses: UART.
39D7Digital_IOSignal terminal D7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D7. Supported peripheral buses: General.
40D6Digital_IOSignal terminal D6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D6. Supported peripheral buses: General.
41D5Digital_IOSignal terminal D5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D5. Supported peripheral buses: General.
42D4Digital_IOSignal terminal D4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D4. Supported peripheral buses: General.
43D3Digital_IOSignal terminal D3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D3. Supported peripheral buses: General.
44D2Digital_IOSignal terminal D2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D2. Supported peripheral buses: General.
45D1Digital_IOSignal terminal D1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D1. Supported peripheral buses: General.
46D0Digital_IOSignal terminal D0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D0. Supported peripheral buses: General.
47VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
48GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
49VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
50TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
51RTS0Digital_IOSignal terminal RTS0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS0. Supported peripheral buses: UART.
52DTR0Digital_IOSignal terminal DTR0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR0. Supported peripheral buses: UART.
53TXD1Digital_IOSignal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
54RTS1Digital_IOSignal terminal RTS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS1. Supported peripheral buses: UART.
55DTR1Digital_IOSignal terminal DTR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR1. Supported peripheral buses: UART.
56PECKP/PECKNDigital_IOSignal terminal PECKP/PECKN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PECKP/PECKN. Supported peripheral buses: General.
57STBDigital_IOSignal terminal STB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: STB. Supported peripheral buses: General.
58AFDDigital_IOSignal terminal AFD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AFD. Supported peripheral buses: General.
59SINDigital_IOSignal terminal SIN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SIN. Supported peripheral buses: General.
60INITDigital_IOSignal terminal INIT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INIT. Supported peripheral buses: General.
61GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
62MDPRT#Digital_IOSignal terminal MDPRT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDPRT#. Supported peripheral buses: General.
63MDSELDigital_IOSignal terminal MDSEL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDSEL. Supported peripheral buses: General.
64CKSELDigital_IOSignal terminal CKSEL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CKSEL. Supported peripheral buses: General.
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