ChipDocs.org
⌘K
2284 PARTSUpload PDF
CH9120 (QFN-28-EP(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9120

WCHID: C2681747QFN-28-EP(4x4) · 29 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9120 (QFN-28-EP(4x4))1NC2NC3VCC4VCC5VDD6RXD7TXD8RXP9RXN10TXP11TXN12NC13NC14ACT15LINK29EPAD/GND28TCPCS27RESET26CFG025RS485DIR24NC23CFGEN22VCC21NC20VREF19XI18XO17RUN16RSTIGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.225.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829E=4.00mm · Pitch e=0.50mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1NCI/OMultiplexed I/O & Peripheral Pin NC (General)
2NCI/OMultiplexed I/O & Peripheral Pin NC (General)
3VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
4VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
5VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
6RXDI/OMultiplexed I/O & Peripheral Pin RXD (UART)
7TXDI/OMultiplexed I/O & Peripheral Pin TXD (UART)
8RXPI/OMultiplexed I/O & Peripheral Pin RXP (General)
9RXNI/OMultiplexed I/O & Peripheral Pin RXN (General)
10TXPI/OMultiplexed I/O & Peripheral Pin TXP (General)
11TXNI/OMultiplexed I/O & Peripheral Pin TXN (General)
12NCI/OMultiplexed I/O & Peripheral Pin NC (General)
13NCI/OMultiplexed I/O & Peripheral Pin NC (General)
14ACTI/OMultiplexed I/O & Peripheral Pin ACT (General)
15LINKI/OMultiplexed I/O & Peripheral Pin LINK (General)
16RSTII/OMultiplexed I/O & Peripheral Pin RSTI (General)
17RUNISystem Enable & Hardware Reset (RUN)
18XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
19XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
20VREFAnalogMultiplexed I/O & Peripheral Pin VREF (General)
21NCI/OMultiplexed I/O & Peripheral Pin NC (General)
22VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
23CFGENI/OMultiplexed I/O & Peripheral Pin CFGEN (General)
24NCI/OMultiplexed I/O & Peripheral Pin NC (General)
25RS485DIRI/OMultiplexed I/O & Peripheral Pin RS485DIR (General)
26CFG0I/OMultiplexed I/O & Peripheral Pin CFG0 (General)
27RESETISystem Enable & Hardware Reset (RESET)
28TCPCSI/OMultiplexed I/O & Peripheral Pin TCPCS (General)
29EPAD/GNDGNDGround Reference Pin (EPAD/GND)
PIN 1 NC
I/O
Multiplexed I/O & Peripheral Pin NC (General)
Design note: Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 3 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9120 (WCH · QFN-28-EP(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9120 (QFN-28-EP(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9120 (QFN-28-EP(4x4)) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9120 (QFN-28-EP(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9120 (QFN-28-EP(4x4)) - 4. Package Dimensions (D×E×A)
QFN-28-EP(4x4) · 4.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9120 (QFN-28-EP(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9120 (QFN-28-EP(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (3 figures · Page 1/1)
Showing 1–3 of 3 uncropped original figures for CH9120
P1 · p01_fig011251×778px
CH9120 (QFN-28-EP(4x4)) — 2. Features
2. Features
P2 · p02_fig01736×720px
CH9120 (QFN-28-EP(4x4)) — Package
Package
P2 · p02_fig01P2
CH9120 (QFN-28-EP(4x4)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)

Technical Specifications & Part Details (CH9120)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9120 (QFN-28-EP(4x4)) is a 28-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-28-EP(4x4))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 2.56×2.56mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-28-EP(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-28-EP(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9120 (QFN-28-EP(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9120 (QFN-28-EP(4x4))?

Manufactured by WCH, the CH9120 is housed in a QFN-28-EP(4x4) package with 29 pins and a 0.50 mm lead pitch. Key pins include: 1 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 2 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 3 (VCC: Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)), 4 (VCC: Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)), 5 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), 6 (RXD: Multiplexed I/O & Peripheral Pin RXD (UART)).

What are the IPC-7351B PCB Footprint dimensions for CH9120?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9120 (QFN-28-EP(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 2.56 × 2.56 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9120?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9120 (WCH, QFN-28-EP(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & CH9120 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
2NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
3VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
5VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
6RXDDigital_IOSignal terminal RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART.
7TXDDigital_IOSignal terminal TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
8RXPDigital_IOSignal terminal RXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXP. Supported peripheral buses: General.
9RXNDigital_IOSignal terminal RXN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXN. Supported peripheral buses: General.
10TXPDigital_IOSignal terminal TXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXP. Supported peripheral buses: General.
11TXNDigital_IOSignal terminal TXN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXN. Supported peripheral buses: General.
12NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
13NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
14ACTDigital_IOSignal terminal ACT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ACT. Supported peripheral buses: General.
15LINKDigital_IOSignal terminal LINK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LINK. Supported peripheral buses: General.
16RSTIDigital_IOSignal terminal RSTI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSTI. Supported peripheral buses: General.
17RUNDigital_IOActive-low hardware reset terminal (RUN): pulling this pin Low resets the processor core and peripherals.
18XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
19XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
20VREFAnalogSignal terminal VREF (Analog, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VREF. Supported peripheral buses: General.
21NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
22VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
23CFGENDigital_IOSignal terminal CFGEN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFGEN. Supported peripheral buses: General.
24NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
25RS485DIRDigital_IOSignal terminal RS485DIR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RS485DIR. Supported peripheral buses: General.
26CFG0Digital_IOSignal terminal CFG0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG0. Supported peripheral buses: General.
27RESETDigital_IOActive-low hardware reset terminal (RESET): pulling this pin Low resets the processor core and peripherals.
28TCPCSDigital_IOSignal terminal TCPCS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TCPCS. Supported peripheral buses: General.
29EPAD/GNDGND0V electrical ground return terminal (EPAD/GND) for internal core logic, I/O drivers, and analog sub-blocks.
ExplorePartsPackagesMFRsUpload