AT86RF233-ZUR (QFN-32-EP(5x5)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of AT86RF233-ZUR (QFN-32-EP(5x5))?

Manufactured by MICROCHIP, the AT86RF233-ZUR is housed in a QFN-32-EP(5x5) package with 33 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.8V to 3.6V. Key pins include: 1 (DIG3: Multiplexed I/O & Peripheral Pin DIG3 (General)), 2 (DIG4: Multiplexed I/O & Peripheral Pin DIG4 (General)), 3 (AVSS: Ground Reference Pin (AVSS)), 4 (RFP: Multiplexed I/O & Peripheral Pin RFP (General)), 5 (RFN: Multiplexed I/O & Peripheral Pin RFN (General)), 6 (AVSS: Ground Reference Pin (AVSS)).

Q: What are the IPC-7351B PCB Footprint dimensions for AT86RF233-ZUR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT86RF233-ZUR (QFN-32-EP(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 3.20 × 3.20 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT86RF233-ZUR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT86RF233-ZUR (MICROCHIP, QFN-32-EP(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	DIG3	I/O	Multiplexed I/O & Peripheral Pin DIG3 (General)
2	DIG4	I/O	Multiplexed I/O & Peripheral Pin DIG4 (General)
3	AVSS	GND	Ground Reference Pin (AVSS)
4	RFP	I/O	Multiplexed I/O & Peripheral Pin RFP (General)
5	RFN	I/O	Multiplexed I/O & Peripheral Pin RFN (General)
6	AVSS	GND	Ground Reference Pin (AVSS)
7	DVSS	GND	Ground Reference Pin (DVSS)
8	RST#	I/O	Multiplexed I/O & Peripheral Pin RST# (General)
9	DIG1	I/O	Multiplexed I/O & Peripheral Pin DIG1 (General)
10	DIG2	I/O	Multiplexed I/O & Peripheral Pin DIG2 (General)
11	SLP_TR	I/O	Multiplexed I/O & Peripheral Pin SLP_TR (General)
12	DVSS	GND	Ground Reference Pin (DVSS)
13	DVDD	Power	Power Supply Input (DVDD — 1.8V to 3.6V)
14	DVDD	Power	Power Supply Input (DVDD — 1.8V to 3.6V)
15	DEVDD	Power	Power Supply Input (DEVDD — 1.8V to 3.6V)
16	DVSS	GND	Ground Reference Pin (DVSS)
17	CLKM	I/O	Multiplexed I/O & Peripheral Pin CLKM (General)
18	DVSS	GND	Ground Reference Pin (DVSS)
19	SCLK	I/O	Multiplexed I/O & Peripheral Pin SCLK (SPI, I2C)
20	MISO	I/O	Multiplexed I/O & Peripheral Pin MISO (SPI)
21	DVSS	GND	Ground Reference Pin (DVSS)
22	MOSI	I/O	Multiplexed I/O & Peripheral Pin MOSI (SPI)
23	SEL#	I/O	Multiplexed I/O & Peripheral Pin SEL# (General)
24	IRQ	I/O	Multiplexed I/O & Peripheral Pin IRQ (General)
25	XTAL2	I/O	Multiplexed I/O & Peripheral Pin XTAL2 (RTC/CLK)
26	XTAL1	I/O	Multiplexed I/O & Peripheral Pin XTAL1 (RTC/CLK)
27	AVSS	GND	Ground Reference Pin (AVSS)
28	EVDD	Power	Power Supply Input (EVDD — 1.8V to 3.6V)
29	AVDD	Power	Power Supply Input (AVDD — 1.8V to 3.6V)
30	AVSS	GND	Ground Reference Pin (AVSS)
31	AVSS	GND	Ground Reference Pin (AVSS)
32	AVSS	GND	Ground Reference Pin (AVSS)
33	AVSS	GND	Ground Reference Pin (AVSS)

PIN 1 DIG3

I/O

Multiplexed I/O & Peripheral Pin DIG3 (General)

Design note: Signal terminal DIG3 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: DIG3. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

AT86RF233-ZUR (QFN-32-EP(5x5)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

AT86RF233-ZUR (QFN-32-EP(5x5)) - 2. Standard Pinout (Top View)

True package pinout (33 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

AT86RF233-ZUR (QFN-32-EP(5x5)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

AT86RF233-ZUR (QFN-32-EP(5x5)) - 4. Package Dimensions (D×E×A)

QFN-32-EP(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

AT86RF233-ZUR (QFN-32-EP(5x5)) - 5. Recommended Land Pattern

IPC-7351B Footprint (33 Pads)Expand ›

6. Application SchematicSCHEMATIC

AT86RF233-ZUR (QFN-32-EP(5x5)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)

Showing 1–6 of 6 uncropped original figures for AT86RF233

P8 · p08_fig012043×2422px

MCU Wireless AT86RF233 [PRELIMINARY DATASHEET] Atmel-8351E-MCU_Wireless-AT86RF233_Datasheet_072014 8

P15 · p15_fig011365×1216px

Figure 5-1. Basic Application Schematic.

P17 · p17_fig011647×1214px

Figure 5-2. Extended Feature Application Schematic.

P17 · p17_fig01P17

Datasheet Page 17 (p17_fig01)

P127 · p127_fig011085×874px

Figure 9-14. Simplified XOSC Schematic with External Components.

P225 · p225_fig012056×980px

AT86RF233-ZUR (QFN-32-EP(5x5)) — Altmel | Enabling Unlimited Possibilities BOs wv Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2014 Atmel Corporation. / Rev.:Atmel-8351E-MCU_Wireless-AT86RF233

Altmel | Enabling Unlimited Possibilities BOs wv Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2014 Atmel Corporation. / Rev.:Atmel-8351E-MCU_Wireless-AT86RF233

Technical Specifications & Part Details (AT86RF233-ZUR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:AT86RF233-ZUR (QFN-32-EP(5x5)) is a 32-pin standard electronic & interconnect component featuring a 5.00 × 5.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V to 3.6V supply operation across -40°C to +85°C with integrated SPI, I2C, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V to 3.6V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to +85°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

2.4GHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

5.00 × 5.00 × 0.85 mm (A1=0.03 mm)

Package family: QFN (QFN-32-EP(5x5))

Pin Count & Lead PitchN / e

32 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

SPI, I2C, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol33 auto-grouped pins

IPC-7351B Land Pattern33 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteEPAD 3.20×3.20mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-32-EP(5x5))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

5.00 × 5.00 mm

Height (A) & Pitch (e)IPC-7351B

A=0.85mm · e=0.50mm

Pad Size (W × L)Level B

0.28 × 0.80 mm

Pins / Total PadsTopology

33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit QFN-32-EP(5x5)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — AT86RF233-ZUR (QFN-32-EP(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of AT86RF233-ZUR (QFN-32-EP(5x5))?

Manufactured by MICROCHIP, the AT86RF233-ZUR is housed in a QFN-32-EP(5x5) package with 33 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.8V to 3.6V. Key pins include: 1 (DIG3: Multiplexed I/O & Peripheral Pin DIG3 (General)), 2 (DIG4: Multiplexed I/O & Peripheral Pin DIG4 (General)), 3 (AVSS: Ground Reference Pin (AVSS)), 4 (RFP: Multiplexed I/O & Peripheral Pin RFP (General)), 5 (RFN: Multiplexed I/O & Peripheral Pin RFN (General)), 6 (AVSS: Ground Reference Pin (AVSS)).

What are the IPC-7351B PCB Footprint dimensions for AT86RF233-ZUR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT86RF233-ZUR (QFN-32-EP(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 3.20 × 3.20 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT86RF233-ZUR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT86RF233-ZUR (MICROCHIP, QFN-32-EP(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & AT86RF233 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	DIG3	Digital_IO	Signal terminal DIG3 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: DIG3. Supported peripheral buses: General.
2	DIG4	Digital_IO	Signal terminal DIG4 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: DIG4. Supported peripheral buses: General.
3	AVSS	GND	0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
4	RFP	RF_50Ohm	Signal terminal RFP (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RFP. Supported peripheral buses: General.
5	RFN	RF_50Ohm	Signal terminal RFN (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RFN. Supported peripheral buses: General.
6	AVSS	GND	0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
7	DVSS	GND	0V electrical ground return terminal (DVSS) for internal core logic, I/O drivers, and analog sub-blocks.
8	RST#	Digital_IO	Signal terminal RST# (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RST#. Supported peripheral buses: General.
9	DIG1	Digital_IO	Signal terminal DIG1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: DIG1. Supported peripheral buses: General.
10	DIG2	Digital_IO	Signal terminal DIG2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: DIG2. Supported peripheral buses: General.
11	SLP_TR	Digital_IO	Signal terminal SLP_TR (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: SLP_TR. Supported peripheral buses: General.
12	DVSS	GND	0V electrical ground return terminal (DVSS) for internal core logic, I/O drivers, and analog sub-blocks.
13	DVDD	Power_In	Primary positive power supply input (DVDD) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
14	DVDD	Power_In	Primary positive power supply input (DVDD) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
15	DEVDD	Power_In	Primary positive power supply input (DEVDD) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
16	DVSS	GND	0V electrical ground return terminal (DVSS) for internal core logic, I/O drivers, and analog sub-blocks.
17	CLKM	Digital_IO	Signal terminal CLKM (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: CLKM. Supported peripheral buses: General.
18	DVSS	GND	0V electrical ground return terminal (DVSS) for internal core logic, I/O drivers, and analog sub-blocks.
19	SCLK	Digital_IO	Signal terminal SCLK (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: SCLK. Supported peripheral buses: SPI, I2C.
20	MISO	Digital_IO	Signal terminal MISO (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: MISO. Supported peripheral buses: SPI.
21	DVSS	GND	0V electrical ground return terminal (DVSS) for internal core logic, I/O drivers, and analog sub-blocks.
22	MOSI	Digital_IO	Signal terminal MOSI (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: MOSI. Supported peripheral buses: SPI.
23	SEL#	Digital_IO	Signal terminal SEL# (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: SEL#. Supported peripheral buses: General.
24	IRQ	Digital_IO	Signal terminal IRQ (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: IRQ. Supported peripheral buses: General.
25	XTAL2	Digital_IO	Signal terminal XTAL2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: XTAL2. Supported peripheral buses: RTC/CLK.
26	XTAL1	Digital_IO	Signal terminal XTAL1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: XTAL1. Supported peripheral buses: RTC/CLK.
27	AVSS	GND	0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
28	EVDD	Power_In	Primary positive power supply input (EVDD) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
29	AVDD	Power_In	Primary positive power supply input (AVDD) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
30	AVSS	GND	0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
31	AVSS	GND	0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
32	AVSS	GND	0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
33	AVSS	GND	0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.

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