APA300-FG144I (FPBGA-144) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of APA300-FG144I (FPBGA-144)?

Manufactured by MICROCHIP, the APA300-FG144I is housed in a FPBGA-144 package with 144 pins and a 1.00 mm lead pitch. Key pins include: A1 (I/O: Multiplexed I/O & Peripheral Pin I/O (General)), A2 (I/O: Multiplexed I/O & Peripheral Pin I/O (General)), A3 (I/O: Multiplexed I/O & Peripheral Pin I/O (General)), A4 (I/O: Multiplexed I/O & Peripheral Pin I/O (General)), A5 (I/O: Multiplexed I/O & Peripheral Pin I/O (General)), A6 (GND: Ground Reference Pin (GND)).

Q: What are the IPC-7351B PCB Footprint dimensions for APA300-FG144I?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), APA300-FG144I (FPBGA-144) has a nominal body envelope of 13.00 × 13.00 mm, pitch e = 1.00 mm, and 144 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for APA300-FG144I?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for APA300-FG144I (MICROCHIP, FPBGA-144) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 13.00mm × 13.00mm · Pitch: 1.00mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (144/144)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
A1	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
A2	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
A3	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
A4	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
A5	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
A6	GND	GND	Ground Reference Pin (GND)
A7	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
A8	VDD	Power	Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
A9	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
A10	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
A11	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
A12	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
B1	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
B2	GND	GND	Ground Reference Pin (GND)
B3	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
B4	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
B5	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
B6	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
B7	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
B8	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
B9	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
B10	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
B11	GND	GND	Ground Reference Pin (GND)
B12	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
C1	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
C2	I/O/GL1	I/O	Multiplexed I/O & Peripheral Pin I/O/GL1 (General)
C3	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
C4	VDD	Power	Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
C5	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
C6	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
C7	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
C8	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
C9	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
C10	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
C11	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
C12	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
D1	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
D2	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
D3	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
D4	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
D5	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
D6	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
D7	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
D8	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
D9	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
D10	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
D11	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
D12	I/O/GLMX2	I/O	Multiplexed I/O & Peripheral Pin I/O/GLMX2 (General)
E1	VDD	Power	Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
E2	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
E3	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
E4	VDDP	Power	Power Supply Input (VDDP — 3.3V / 5.0V Standard Logic)
E5	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
E6	VDDP	Power	Power Supply Input (VDDP — 3.3V / 5.0V Standard Logic)
E7	VDDP	Power	Power Supply Input (VDDP — 3.3V / 5.0V Standard Logic)
E8	AVDD	Power	Power Supply Input (AVDD — 3.3V / 5.0V Standard Logic)
E9	VDDP	Power	Power Supply Input (VDDP — 3.3V / 5.0V Standard Logic)
E10	VDD	Power	Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
E11	NPECL2	I/O	Multiplexed I/O & Peripheral Pin NPECL2 (General)
E12	AGND	GND	Ground Reference Pin (AGND)
F1	I/O/GL2	I/O	Multiplexed I/O & Peripheral Pin I/O/GL2 (General)
F2	AGND	GND	Ground Reference Pin (AGND)
F3	I/O/GLMX1	I/O	Multiplexed I/O & Peripheral Pin I/O/GLMX1 (General)
F4	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
F5	GND	GND	Ground Reference Pin (GND)
F6	GND	GND	Ground Reference Pin (GND)
F7	GND	GND	Ground Reference Pin (GND)
F8	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
F9	I/O/GL4	I/O	Multiplexed I/O & Peripheral Pin I/O/GL4 (General)
F10	GND	GND	Ground Reference Pin (GND)
F11	PPECL2/Input	I/O	Multiplexed I/O & Peripheral Pin PPECL2/Input (General)
F12	I/O/GL3	I/O	Multiplexed I/O & Peripheral Pin I/O/GL3 (General)
G1	PPECL1/Input	I/O	Multiplexed I/O & Peripheral Pin PPECL1/Input (General)
G2	GND	GND	Ground Reference Pin (GND)
G3	AVDD	Power	Power Supply Input (AVDD — 3.3V / 5.0V Standard Logic)
G4	NPECL1	I/O	Multiplexed I/O & Peripheral Pin NPECL1 (General)
G5	GND	GND	Ground Reference Pin (GND)
G6	GND	GND	Ground Reference Pin (GND)
G7	GND	GND	Ground Reference Pin (GND)
G8	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
G9	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
G10	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
G11	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
G12	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
H1	VDD	Power	Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
H2	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
H3	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
H4	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
H5	VDD	Power	Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
H6	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
H7	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
H8	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
H9	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
H10	VDDP	Power	Power Supply Input (VDDP — 3.3V / 5.0V Standard Logic)
H11	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
H12	VDD	Power	Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
J1	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
J2	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
J3	VDDP	Power	Power Supply Input (VDDP — 3.3V / 5.0V Standard Logic)
J4	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
J5	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
J6	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
J7	VDD	Power	Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
J8	TCK	I/O	Multiplexed I/O & Peripheral Pin TCK (General)
J9	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
J10	TDO	I/O	Multiplexed I/O & Peripheral Pin TDO (General)
J11	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
J12	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
K1	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
K2	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
K3	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
K4	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
K5	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
K6	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
K7	GND	GND	Ground Reference Pin (GND)
K8	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
K9	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
K10	GND	GND	Ground Reference Pin (GND)
K11	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
K12	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
L1	GND	GND	Ground Reference Pin (GND)
L2	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
L3	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
L4	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
L5	VDDP	Power	Power Supply Input (VDDP — 3.3V / 5.0V Standard Logic)
L6	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
L7	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
L8	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
L9	TMS	I/O	Multiplexed I/O & Peripheral Pin TMS (General)
L10	RCK	I/O	Multiplexed I/O & Peripheral Pin RCK (General)
L11	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
L12	TRST	I/O	Multiplexed I/O & Peripheral Pin TRST (General)
M1	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
M2	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
M3	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
M4	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
M5	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
M6	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
M7	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
M8	I/O	I/O	Multiplexed I/O & Peripheral Pin I/O (General)
M9	TDI	I/O	Multiplexed I/O & Peripheral Pin TDI (General)
M10	VDDP	Power	Power Supply Input (VDDP — 3.3V / 5.0V Standard Logic)
M11	VPP	I/O	Multiplexed I/O & Peripheral Pin VPP (General)
M12	VPN	I/O	Multiplexed I/O & Peripheral Pin VPN (General)

PIN A1 I/O

I/O

Multiplexed I/O & Peripheral Pin I/O (General)

Design note: Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 3 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

APA300-FG144I (FPBGA-144) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

APA300-FG144I (FPBGA-144) - 2. Standard Pinout (Top View)

True package pinout (144 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

APA300-FG144I (FPBGA-144) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

APA300-FG144I (FPBGA-144) - 4. Package Dimensions (D×E×A)

FPBGA-144 · 13.00×13.00mm · Pitch 1.00mmExpand ›

5. Recommended Land PatternLAND PATTERN

APA300-FG144I (FPBGA-144) - 5. Recommended Land Pattern

IPC-7351B Footprint (144 Pads)Expand ›

6. Application SchematicSCHEMATIC

APA300-FG144I (FPBGA-144) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (3 figures · Page 1/1)

Showing 1–3 of 3 uncropped original figures for APA150 / APA300 / APA1000

P1 · p01_fig011975×527px

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P2 · p02_fig011832×1316px

Ordering Information

P10 · p10_fig01686×312px

All other trademarks are the property of their owners.

Technical Specifications & Part Details (APA300-FG144I)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:APA300-FG144I (FPBGA-144) is a 144-pin standard electronic & interconnect component featuring a 13.00 × 13.00 × 1.35 mm mechanical envelope (lead pitch e = 1.00 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across 0°C to +70°C with integrated JTAG / SWD interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V ~ 5.5V (Theo Datasheet)

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

0°C to +70°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

50 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

13.00 × 13.00 × 1.35 mm (A1=0.30 mm)

Package family: BGA (FPBGA-144)

Pin Count & Lead PitchN / e

144 Pins | Pitch e = 1.00 mm (39.4 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

JTAG / SWD

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol144 auto-grouped pins

IPC-7351B Land Pattern144 pads · Pitch 1.00mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (FPBGA-144)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

13.00 × 13.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.35mm · e=1.00mm

Pad Size (W × L)Level B

0.32 × 0.32 mm

Pins / Total PadsTopology

144P / 144Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit FPBGA-144	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — APA300-FG144I (FPBGA-144)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of APA300-FG144I (FPBGA-144)?

Manufactured by MICROCHIP, the APA300-FG144I is housed in a FPBGA-144 package with 144 pins and a 1.00 mm lead pitch. Key pins include: A1 (I/O: Multiplexed I/O & Peripheral Pin I/O (General)), A2 (I/O: Multiplexed I/O & Peripheral Pin I/O (General)), A3 (I/O: Multiplexed I/O & Peripheral Pin I/O (General)), A4 (I/O: Multiplexed I/O & Peripheral Pin I/O (General)), A5 (I/O: Multiplexed I/O & Peripheral Pin I/O (General)), A6 (GND: Ground Reference Pin (GND)).

What are the IPC-7351B PCB Footprint dimensions for APA300-FG144I?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), APA300-FG144I (FPBGA-144) has a nominal body envelope of 13.00 × 13.00 mm, pitch e = 1.00 mm, and 144 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for APA300-FG144I?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for APA300-FG144I (MICROCHIP, FPBGA-144) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (144 pins) & APA150 / APA300 / APA1000 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
A1	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
A2	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
A3	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
A4	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
A5	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
A6	GND	GND	0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
A7	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
A8	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
A9	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
A10	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
A11	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
A12	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
B1	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
B2	GND	GND	0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
B3	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
B4	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
B5	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
B6	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
B7	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
B8	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
B9	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
B10	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
B11	GND	GND	0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
B12	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
C1	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
C2	I/O/GL1	Digital_IO	Signal terminal I/O/GL1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O/GL1. Supported peripheral buses: General.
C3	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
C4	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
C5	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
C6	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
C7	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
C8	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
C9	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
C10	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
C11	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
C12	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
D1	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
D2	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
D3	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
D4	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
D5	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
D6	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
D7	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
D8	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
D9	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
D10	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
D11	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
D12	I/O/GLMX2	Digital_IO	Signal terminal I/O/GLMX2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O/GLMX2. Supported peripheral buses: General.
E1	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
E2	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
E3	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
E4	VDDP	Power_In	Primary positive power supply input (VDDP) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
E5	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
E6	VDDP	Power_In	Primary positive power supply input (VDDP) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
E7	VDDP	Power_In	Primary positive power supply input (VDDP) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
E8	AVDD	Power_In	Primary positive power supply input (AVDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
E9	VDDP	Power_In	Primary positive power supply input (VDDP) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
E10	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
E11	NPECL2	Digital_IO	Signal terminal NPECL2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NPECL2. Supported peripheral buses: General.
E12	AGND	GND	0V electrical ground return terminal (AGND) for internal core logic, I/O drivers, and analog sub-blocks.
F1	I/O/GL2	Digital_IO	Signal terminal I/O/GL2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O/GL2. Supported peripheral buses: General.
F2	AGND	GND	0V electrical ground return terminal (AGND) for internal core logic, I/O drivers, and analog sub-blocks.
F3	I/O/GLMX1	Digital_IO	Signal terminal I/O/GLMX1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O/GLMX1. Supported peripheral buses: General.
F4	I/O	Digital_IO	Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.

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