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STM32U083KCU6 (UFQFPN-32-EP(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32U083KCU6

STID: C22459164UFQFPN-32-EP(5x5) · 33 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32U083KCU6 (UFQFPN-32-EP(5x5))1VDD2PC14-OSC32_I3PC15-OSC32_O4PF2-NRST5VDDA/VREF+6PA0-CK_IN7PA18PA29PA310PA411PA512PA613PA714PB015PB116VSS17VDD33EP32VSS31PF3-BOOT030PB729PB628PB527PB426PB325PA1524PA1423PA1322PA12[PA10]21PA11[PA9]20PA1019PA918PA8Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.827.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233E=5.00mm · Pitch e=0.50mmD=5.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
2PC14-OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
3PC15-OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)
4PF2-NRSTI/OMultiplexed I/O & Peripheral Pin PF2-NRST (General)
5VDDA/VREF+PowerPower Supply Input (VDDA/VREF+ — 3.3V VDD (Max 4.0V))
6PA0-CK_INI/OMultiplexed I/O & Peripheral Pin PA0-CK_IN (General)
7PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
8PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
9PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
10PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
11PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
12PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
13PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
14PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
15PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
16VSSGNDGround Reference Pin (VSS)
17VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
18PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
19PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
20PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
21PA11[PA9]I/OMultiplexed I/O & Peripheral Pin PA11[PA9] (General)
22PA12[PA10]I/OMultiplexed I/O & Peripheral Pin PA12[PA10] (General)
23PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
24PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
25PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
26PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
27PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
28PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
29PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
30PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
31PF3-BOOT0I/OMultiplexed I/O & Peripheral Pin PF3-BOOT0 (General)
32VSSGNDGround Reference Pin (VSS)
33EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 VDD
Power
Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 16 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32U083KCU6 (ST · UFQFPN-32-EP(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32U083KCU6 (UFQFPN-32-EP(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32U083KCU6 (UFQFPN-32-EP(5x5)) - 2. Standard Pinout (Top View)
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32U083KCU6 (UFQFPN-32-EP(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32U083KCU6 (UFQFPN-32-EP(5x5)) - 4. Package Dimensions (D×E×A)
UFQFPN-32-EP(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32U083KCU6 (UFQFPN-32-EP(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32U083KCU6 (UFQFPN-32-EP(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (16 figures · Page 1/2)
Showing 1–12 of 16 uncropped original figures for STM32U083
P1 · p01_fig01EXACT PACKAGE
STM32U083KCU6 (UFQFPN-32-EP(5x5)) — 特性 包括意法半导体最先进的专利技术。 超低功耗特性（超低功耗器件） LOFP48 UFQFPN32 (7x7 mm) (6x 5mm) LOQFP64 UFQFPN48 (10 x 10 mm) (7x 7mm) LQFP80 (12 x 12 mm) “| ea UFBGA64 WLCSP42 (5x5 mm) (2.82 x 2.93 mm) UFBGA81 (5x5 mm)
特性 包括意法半导体最先进的专利技术。 超低功耗特性（超低功耗器件） LOFP48 UFQFPN32 (7x7 mm) (6x 5mm) LOQFP64 UFQFPN48 (10 x 10 mm) (7x 7mm) LQFP80 (12 x 12 mm) “| ea UFBGA64 WLCSP42 (5x5 mm) (2.82 x 2.93 mm) UFBGA81 (5x5 mm)
P1 · p01_fig02EXACT PACKAGE
STM32U083KCU6 (UFQFPN-32-EP(5x5)) — 产品摘要 | STM32U083xC | STM32U083KC、 STM32U083HC、 STM32U083CC、 STM32U083RC、 STM32U083MC | 产品标签
产品摘要 | STM32U083xC | STM32U083KC、 STM32U083HC、 STM32U083CC、 STM32U083RC、 STM32U083MC | 产品标签
P25 · p25_fig01EXACT PACKAGE
STM32U083KCU6 (UFQFPN-32-EP(5x5)) — 图 3. UFQFPN32引脚排列
图 3. UFQFPN32引脚排列
P30 · p30_fig01EXACT PACKAGE
STM32U083KCU6 (UFQFPN-32-EP(5x5)) — STM32U031x4/6/8 引脚排列/焊球布局、引脚说明和复用功能 | 引脚号 | 引脚名 （复位后的功能） | 引脚类型 | I/O 结构 | 备注 复用功能 其他功能 | UFQFPN32 | WLCSP42 | LQFP48 | UFQFPN48 | LQFP64 | UFBGA64 | LQFP80 | UFBGA81 | 4 E12 7 7 7 E1 9 E2 PF2-NRST I/O RST - MCO NRST | - - - - 8 E3 10 E1 PC
STM32U031x4/6/8 引脚排列/焊球布局、引脚说明和复用功能 | 引脚号 | 引脚名 （复位后的功能） | 引脚类型 | I/O 结构 | 备注 复用功能 其他功能 | UFQFPN32 | WLCSP42 | LQFP48 | UFQFPN48 | LQFP64 | UFBGA64 | LQFP80 | UFBGA81 | 4 E12 7 7 7 E1 9 E2 PF2-NRST I/O RST - MCO NRST | - - - - 8 E3 10 E1 PC
P32 · p32_fig01EXACT PACKAGE
STM32U083KCU6 (UFQFPN-32-EP(5x5)) — STM32U031x4/6/8 引脚排列/焊球布局、引脚说明和复用功能 | DS14463 - Rev 2 page 32/138 | 引脚号 | 引脚名 （复位后的功能） | 引脚类型 | I/O 结构 | 备注 复用功能 其他功能 | UFQFPN32 | WLCSP42 | LQFP48 | UFQFPN48 | LQFP64 | UFBGA64 | LQFP80 | UFBGA81 | - - 28 28 36 F7 42 F7 PB15 I/O FT_l - | R
STM32U031x4/6/8 引脚排列/焊球布局、引脚说明和复用功能 | DS14463 - Rev 2 page 32/138 | 引脚号 | 引脚名 （复位后的功能） | 引脚类型 | I/O 结构 | 备注 复用功能 其他功能 | UFQFPN32 | WLCSP42 | LQFP48 | UFQFPN48 | LQFP64 | UFBGA64 | LQFP80 | UFBGA81 | - - 28 28 36 F7 42 F7 PB15 I/O FT_l - | R
P33 · p33_fig01EXACT PACKAGE
STM32U083KCU6 (UFQFPN-32-EP(5x5)) — STM32U031x4/6/8 引脚排列/焊球布局、引脚说明和复用功能 | DS14463 - Rev 2 page 33/138 | 引脚号 | 引脚名 （复位后的功能） | 引脚类型 | I/O 结构 | 备注 复用功能 其他功能 | UFQFPN32 | WLCSP42 | LQFP48 | UFQFPN48 | LQFP64 | UFBGA64 | LQFP80 | UFBGA81 | - B1 36 36 48 E5 60 C7 VDDUSB S - - - - |
STM32U031x4/6/8 引脚排列/焊球布局、引脚说明和复用功能 | DS14463 - Rev 2 page 33/138 | 引脚号 | 引脚名 （复位后的功能） | 引脚类型 | I/O 结构 | 备注 复用功能 其他功能 | UFQFPN32 | WLCSP42 | LQFP48 | UFQFPN48 | LQFP64 | UFBGA64 | LQFP80 | UFBGA81 | - B1 36 36 48 E5 60 C7 VDDUSB S - - - - |
P107 · p107_fig01EXACT PACKAGE
STM32U083KCU6 (UFQFPN-32-EP(5x5)) — 图 35. UFQFPN32 - 封装尺寸示例
图 35. UFQFPN32 - 封装尺寸示例
P107 · p107_fig02EXACT PACKAGE
STM32U083KCU6 (UFQFPN-32-EP(5x5)) — 图 35. UFQFPN32 - 封装尺寸示例
图 35. UFQFPN32 - 封装尺寸示例
P127 · p127_fig02EXACT PACKAGE
STM32U083KCU6 (UFQFPN-32-EP(5x5)) — PI/O =∑(VOL × IOL)+ ∑((VDDIOx - VOH ))× IOH 考虑了应用中 I/O 在低电平和高电平状态下的实际 VOL/IOL 和 VOH/IOH。
PI/O =∑(VOL × IOL)+ ∑((VDDIOx - VOH ))× IOH 考虑了应用中 I/O 在低电平和高电平状态下的实际 VOL/IOL 和 VOH/IOH。
P1 · p01_fig03526×373px
STM32U083KCU6 (UFQFPN-32-EP(5x5)) — 产品标签
产品标签
P1 · p01_fig03P1
STM32U083KCU6 (UFQFPN-32-EP(5x5)) — Datasheet Page 1 (p01_fig03)
Datasheet Page 1 (p01_fig03)
P25 · p25_fig021469×597px
STM32U083KCU6 (UFQFPN-32-EP(5x5)) — 图 4. WLCSP42 焊球布局
图 4. WLCSP42 焊球布局
Page 1 / 2 (16 extracted figures)

Technical Specifications & Part Details (STM32U083KCU6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32U083KCU6 (UFQFPN-32-EP(5x5)) is a 32-pin embedded microcontroller unit (mcu) featuring a 5.00 × 5.00 × 0.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
56 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.60 mm (A1=0.03 mm)
Package family: QFN (UFQFPN-32-EP(5x5))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PF3-BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol33 auto-grouped pins
OK
IPC-7351B Land Pattern33 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 3.45×3.45mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFQFPN-32-EP(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.60mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFQFPN-32-EP(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32U083KCU6 (UFQFPN-32-EP(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32U083KCU6 (UFQFPN-32-EP(5x5))?

Manufactured by ST, the STM32U083KCU6 is housed in a UFQFPN-32-EP(5x5) package with 33 pins and a 0.50 mm lead pitch. Key pins include: 1 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), 2 (PC14-OSC32_IN: Multiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)), 3 (PC15-OSC32_OUT: Multiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)), 4 (PF2-NRST: Multiplexed I/O & Peripheral Pin PF2-NRST (General)), 5 (VDDA/VREF+: Power Supply Input (VDDA/VREF+ — 3.3V VDD (Max 4.0V))), 6 (PA0-CK_IN: Multiplexed I/O & Peripheral Pin PA0-CK_IN (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32U083KCU6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32U083KCU6 (UFQFPN-32-EP(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 3.45 × 3.45 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32U083KCU6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32U083KCU6 (ST, UFQFPN-32-EP(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & STM32U083 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
2PC14-OSC32_INDigital_IOSignal terminal PC14-OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK.
3PC15-OSC32_OUTDigital_IOSignal terminal PC15-OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK.
4PF2-NRSTDigital_IOSignal terminal PF2-NRST (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2-NRST. Supported peripheral buses: General.
5VDDA/VREF+Power_InPrimary positive power supply input (VDDA/VREF+) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
6PA0-CK_INDigital_IOSignal terminal PA0-CK_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0-CK_IN. Supported peripheral buses: General.
7PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
8PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
9PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
10PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
11PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
12PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
13PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
14PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
15PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
16VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
17VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
18PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
19PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
20PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
21PA11[PA9]Digital_IOSignal terminal PA11[PA9] (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11[PA9]. Supported peripheral buses: General.
22PA12[PA10]Digital_IOSignal terminal PA12[PA10] (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12[PA10]. Supported peripheral buses: General.
23PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
24PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
25PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
26PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
27PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
28PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
29PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
30PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
31PF3-BOOT0Digital_IOSignal terminal PF3-BOOT0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF3-BOOT0. Supported peripheral buses: General.
32VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
33EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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