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CH377F (QFN-28(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH377F

WCHID: C22374969QFN-28(4x4) · 29 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH377F (QFN-28(4x4))1XI2XO3DP34TXD5RXD6XO7XI8SCK9DP110MOSI11CDROM EN/_ G12GPIO113WP14LED15MODE29EP28VDDK27UD-26SD_CMD25SD_SCK24VSDIO23SD_D222GPIO321VCC20GND19GPIO218SD_D117SD_D016SD_CDGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.225.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829E=4.00mm · Pitch e=0.40mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
2XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
3DP3I/OMultiplexed I/O & Peripheral Pin DP3 (General)
4TXDI/OMultiplexed I/O & Peripheral Pin TXD (UART)
5RXDI/OMultiplexed I/O & Peripheral Pin RXD (UART)
6XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
7XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
8SCKI/OMultiplexed I/O & Peripheral Pin SCK (SPI)
9DP1I/OMultiplexed I/O & Peripheral Pin DP1 (General)
10MOSII/OMultiplexed I/O & Peripheral Pin MOSI (SPI)
11CDROM EN/_ GPIO0I/OMultiplexed I/O & Peripheral Pin CDROM EN/_ GPIO0 (General)
12GPIO1I/OMultiplexed I/O & Peripheral Pin GPIO1 (General)
13WPI/OMultiplexed I/O & Peripheral Pin WP (General)
14LEDI/OMultiplexed I/O & Peripheral Pin LED (General)
15MODEI/OMultiplexed I/O & Peripheral Pin MODE (General)
16SD_CDI/OMultiplexed I/O & Peripheral Pin SD_CD (General)
17SD_D0I/OMultiplexed I/O & Peripheral Pin SD_D0 (General)
18SD_D1I/OMultiplexed I/O & Peripheral Pin SD_D1 (General)
19GPIO2I/OMultiplexed I/O & Peripheral Pin GPIO2 (General)
20GNDGNDGround Reference Pin (GND)
21VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
22GPIO3I/OMultiplexed I/O & Peripheral Pin GPIO3 (General)
23SD_D2I/OMultiplexed I/O & Peripheral Pin SD_D2 (General)
24VSDIOI/OMultiplexed I/O & Peripheral Pin VSDIO (General)
25SD_SCKI/OMultiplexed I/O & Peripheral Pin SD_SCK (SPI)
26SD_CMDI/OMultiplexed I/O & Peripheral Pin SD_CMD (General)
27UD-I/OMultiplexed I/O & Peripheral Pin UD- (USB)
28VDDKPowerPower Supply Input (VDDK — 3.3V / 5.0V Standard Logic)
29EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 XI
I/O
Multiplexed I/O & Peripheral Pin XI (RTC/CLK)
Design note: 晶体振荡输入端 ，接外部12MHz 晶体 一端 。
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH377F (WCH · QFN-28(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH377F (QFN-28(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH377F (QFN-28(4x4)) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH377F (QFN-28(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH377F (QFN-28(4x4)) - 4. Package Dimensions (D×E×A)
QFN-28(4x4) · 4.00×4.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH377F (QFN-28(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH377F (QFN-28(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for CH377
P8 · p08_fig01EXACT PACKAGE
CH377F (QFN-28(4x4)) — 7.1 QFN28
7.1 QFN28
P1 · p01_fig011388×1018px
CH377F (QFN-28(4x4)) — 图1-1 芯片应用框图
图1-1 芯片应用框图
P2 · p02_fig011699×958px
CH377F (QFN-28(4x4)) — 4、引脚定义
4、引脚定义
P3 · p03_fig011664×2668px
CH377F (QFN-28(4x4)) — V1.1 3
V1.1 3
P9 · p09_fig011885×1891px
CH377F (QFN-28(4x4)) — 图8-1 是由CH377A 芯片实现的USB 读卡器+3 端口USB2.0 HUB 的参考电路图。
图8-1 是由CH377A 芯片实现的USB 读卡器+3 端口USB2.0 HUB 的参考电路图。
P9 · p09_fig01P9
CH377F (QFN-28(4x4)) — Datasheet Page 9 (p09_fig01)
Datasheet Page 9 (p09_fig01)
P10 · p10_fig011840×1426px
CH377F (QFN-28(4x4)) — 图8-2 是由CH377F 芯片实现的USB 读卡器和串口记录仪的参考电路图。
图8-2 是由CH377F 芯片实现的USB 读卡器和串口记录仪的参考电路图。

Technical Specifications & Part Details (CH377F)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH377F (QFN-28(4x4)) is a 28-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, SDIO, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-28(4x4))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, SDIO, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 2.70×2.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-28(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-28(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH377F (QFN-28(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH377F (QFN-28(4x4))?

Manufactured by WCH, the CH377F is housed in a QFN-28(4x4) package with 29 pins and a 0.40 mm lead pitch. Key pins include: 1 (XI: Multiplexed I/O & Peripheral Pin XI (RTC/CLK)), 2 (XO: Multiplexed I/O & Peripheral Pin XO (RTC/CLK)), 3 (DP3: Multiplexed I/O & Peripheral Pin DP3 (General)), 4 (TXD: Multiplexed I/O & Peripheral Pin TXD (UART)), 5 (RXD: Multiplexed I/O & Peripheral Pin RXD (UART)), 6 (XO: Multiplexed I/O & Peripheral Pin XO (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for CH377F?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH377F (QFN-28(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.40 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 2.70 × 2.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH377F?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH377F (WCH, QFN-28(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & CH377 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
2XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
3DP3Digital_IOSignal terminal DP3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP3. Supported peripheral buses: General.
4TXDDigital_IOSignal terminal TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
5RXDDigital_IOSignal terminal RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART.
6XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
7XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
8SCKDigital_IOSignal terminal SCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI.
9DP1Digital_IOSignal terminal DP1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP1. Supported peripheral buses: General.
10MOSIDigital_IOSignal terminal MOSI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI.
11CDROM EN/_ GPIO0Digital_IOSignal terminal CDROM EN/_ GPIO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO0. Supported peripheral buses: General.
12GPIO1Digital_IOSignal terminal GPIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO1. Supported peripheral buses: General.
13WPDigital_IOSignal terminal WP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WP. Supported peripheral buses: General.
14LEDDigital_IOSignal terminal LED (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED. Supported peripheral buses: General.
15MODEDigital_IOSignal terminal MODE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MODE. Supported peripheral buses: General.
16SD_CDDigital_IOSignal terminal SD_CD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_CD. Supported peripheral buses: General.
17SD_D0Digital_IOSignal terminal SD_D0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_D0. Supported peripheral buses: General.
18SD_D1Digital_IOSignal terminal SD_D1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_D1. Supported peripheral buses: General.
19GPIO2Digital_IOSignal terminal GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO2. Supported peripheral buses: General.
20GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
21VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
22GPIO3Digital_IOSignal terminal GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO3. Supported peripheral buses: General.
23SD_D2Digital_IOSignal terminal SD_D2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_D2. Supported peripheral buses: General.
24VSDIODigital_IOSignal terminal VSDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSDIO. Supported peripheral buses: General.
25SD_SCKDigital_IOSignal terminal SD_SCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI.
26SD_CMDDigital_IOSignal terminal SD_CMD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_CMD. Supported peripheral buses: General.
27UD-Digital_IOSignal terminal UD- (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB.
28VDDKPower_InPrimary positive power supply input (VDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
29EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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