SMD · 61P
Synchronized Pinout (Symbol / 2D / 3D) (65/65)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | GND | GND | Ground Reference Pin (GND) |
| 2 | GND | GND | Ground Reference Pin (GND) |
| 3 | 3V3 | Power | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | NC | NC | No Connect (Leave Floating) |
| 5 | IO2 | I/O | GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1 |
| 6 | IO3 | I/O | GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap) |
| 7 | NC | NC | No Connect (Leave Floating) |
| 8 | IO0 | I/O | GPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin) |
| 9 | IO4 | I/O | GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3 |
| 10 | IO5 | I/O | GPIO5 / RTC_GPIO5 / TOUCH5 / ADC1_CH4 |
| 11 | IO6 | I/O | GPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5 |
| 12 | IO7 | I/O | GPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6 |
| 13 | IO15 | I/O | GPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P |
| 14 | IO16 | I/O | GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N |
| 15 | IO17 | I/O | GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6 |
| 16 | IO18 | I/O | GPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3 |
| 17 | IO8 | I/O | GPIO8 / RTC_GPIO8 / TOUCH8 / ADC1_CH7 / SUBSPICS1 |
| 18 | IO19 | I/O | GPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8 |
| 19 | IO20 | I/O | GPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9 |
| 20 | IO9 | I/O | GPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD |
| 21 | IO10 | I/O | GPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0 |
| 22 | IO11 | I/O | GPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID |
| 23 | IO12 | I/O | GPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK |
| 24 | IO13 | I/O | GPIO13 / RTC_GPIO13 / TOUCH13 / ADC2_CH2 / FSPIQ |
| 25 | IO14 | I/O | GPIO14 / RTC_GPIO14 / TOUCH14 / ADC2_CH3 / FSPIWP |
| 26 | IO21 | I/O | GPIO21 / RTC_GPIO21 |
| 27 | IO47 | I/O | GPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF |
| 28 | IO33 | I/O | GPIO33 / FSPIHD / SUBSPIHD / SPIIO4 |
| 29 | IO34 | I | Input-Only Pin IO34 (SPI) |
| 30 | IO48 | I/O | Multiplexed I/O & Peripheral Pin IO48 (SPI) |
| 31 | IO35 | I | Input-Only Pin IO35 (SPI) |
| 32 | IO36 | I | Input-Only Pin IO36 (SPI) |
| 33 | IO37 | I | Input-Only Pin IO37 (SPI) |
| 34 | IO38 | I | Input-Only Pin IO38 (SPI) |
| 35 | IO39 | I | Input-Only Pin IO39 (SPI, SWD/JTAG) |
| 36 | IO40 | I/O | Multiplexed I/O & Peripheral Pin IO40 (SWD/JTAG) |
| 37 | IO41 | I/O | Multiplexed I/O & Peripheral Pin IO41 (SWD/JTAG) |
| 38 | IO42 | I/O | Multiplexed I/O & Peripheral Pin IO42 (SWD/JTAG) |
| 39 | TXD0 | I/O | Multiplexed I/O & Peripheral Pin TXD0 (UART) |
| 40 | RXD0 | I/O | Multiplexed I/O & Peripheral Pin RXD0 (UART) |
| 41 | IO45 | I/O | Multiplexed I/O & Peripheral Pin IO45 (General) |
| 42 | GND | GND | Ground Reference Pin (GND) |
| 43 | GND | GND | Ground Reference Pin (GND) |
| 44 | IO46 | I/O | Multiplexed I/O & Peripheral Pin IO46 (General) |
| 45 | EN | I | System Enable & Hardware Reset (EN) |
| 46 | GND | GND | Ground Reference Pin (GND) |
| 47 | GND | GND | Ground Reference Pin (GND) |
| 48 | GND | GND | Ground Reference Pin (GND) |
| 49 | GND | GND | Exposed Thermal & Ground Pad (GND) |
| 50 | GND | GND | Ground Reference Pin (GND) |
| 51 | GND | GND | Ground Reference Pin (GND) |
| 52 | GND | GND | Ground Reference Pin (GND) |
| 53 | GND | GND | Ground Reference Pin (GND) |
| 54 | GND | GND | Ground Reference Pin (GND) |
| 55 | GND | GND | Ground Reference Pin (GND) |
| 56 | GND | GND | Ground Reference Pin (GND) |
| 57 | GND | GND | Exposed Thermal & Ground Pad (GND) |
| 58 | GND | GND | Ground Reference Pin (GND) |
| 59 | GND | GND | Ground Reference Pin (GND) |
| 60 | GND | GND | Ground Reference Pin (GND) |
| 61 | GND | GND | Ground Reference Pin (GND) |
| 62 | GND | GND | Ground Reference Pin (GND) |
| 63 | GND | GND | Ground Reference Pin (GND) |
| 64 | GND | GND | Ground Reference Pin (GND) |
| 65 | GND | GND | Exposed Thermal & Ground Pad (GND) |
PIN 1 GND
GNDGround Reference Pin (GND)
Design note: 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 29 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (65 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SMD,15.4x15.4mm · 15.40×15.40mm · Pitch 0.85mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (73 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (29 figures · Page 1/3)
Showing 1–12 of 29 uncropped original figures for ESP32-S3-MINI
P1 · p01_fig01EXACT PACKAGE
P1 · p01_fig02EXACT PACKAGE
P10 · p10_fig01EXACT PACKAGE
P29 · p29_fig03EXACT PACKAGE
P30 · p30_fig01EXACT PACKAGE
P31 · p31_fig01EXACT PACKAGE
P1 · p01_fig03993×483px
P1 · p01_fig02P1
P10 · p10_fig01P10
P14 · p14_fig01P14
P26 · p26_fig032121×1883px
P27 · p27_fig01P27
Page 1 / 3 (29 extracted figures)
Technical Specifications & Part Details (ESP32-S3-MINI-1U-N4R2)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:ESP32-S3-MINI-1U-N4R2 (SMD,15.4x15.4mm) is a 41-pin wireless wi-fi / bluetooth le soc module featuring a 15.40 × 15.40 × 2.40 mm mechanical envelope (lead pitch e = 0.85 mm). Rated for 3.0 ~ 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Wi-Fi, Bluetooth / BLE, USB, UART, SPI, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0 ~ 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_TX(peak) ≈ 310 mA @ 3.3V | Deep-Sleep ≈ 10 µA | I_GPIO(max) = 40 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
15.40 × 15.40 × 2.40 mm (A1=0.00 mm)
Package family: CASTELLATED_MODULE (SMD,15.4x15.4mm)
Pin Count & Lead PitchN / e
41 Pins | Pitch e = 0.85 mm (33.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, Bluetooth / BLE, USB, UART, SPI, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (Strapping管脚默认配置, Strapping管脚的时序参数说明, 芯片启动模式控制, IO45, IO46): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol65 auto-grouped pins
IPC-7351B Land Pattern73 pads · Pitch 0.85mm
IPC-7525 60% Solder PasteEPAD 4.50×4.50mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.01 PCB Verified
Nguyen Hoang Minh (RF IoT Lab) PCB_VERIFIED
Fabricated 50 units of 4-layer PCBs at JLCPCB with the 15.4x15.4mm LGA footprint and L-shaped shield cutout for U.FL — 100% clean reflow yield.
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — ESP32-S3-MINI (4)
SMD · 61P
SMD,15.4x15.4mm · 65P
65P15.4×15.4×2.40mmP=0.85mm
ESP32-S3-MINI (SMD,15.4x15.4mm)
VFQFN-56-EP · 65P
65P15.4×15.4×2.40mmP=0.85mm
ESP32-S3-MINI (VFQFN-56-EP)
Mechanical Dimensions & Land Pattern (SMD,15.4x15.4mm)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
15.40 × 15.40 mm
Height (A) & Pitch (e)IPC-7351B
A=2.40mm · e=0.85mm
Pad Size (W × L)Level B
0.40 × 0.80 mm
Pins / Total PadsTopology
65P / 73Pad (CASTELLATED_MODULE)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| C1, C2 BOM | 22µF (or 10µF) X5R + 100nF X7R 0805 + 0402 | 3V3 supply decoupling for ~500mA Wi-Fi TX bursts — place closest to 3V3 pin; supply must deliver >= 600mA. |
| R_en + C_en BOM | R = 10kΩ to 3V3 + C = 1µF to GND 0402 / 0603 | Power-On Reset RC delay at EN (CHIP_PU) — 1µF capacitor at EN is REQUIRED for reliable cold boot. |
| R_boot + SW1 BOM | 10kΩ Pull-up + BOOT button 0402 + SMD | Firmware boot-mode strap (IO0 on ESP32/S2/S3, IO9 on ESP32-C3) — on C3 pull IO8 high via 10kΩ for UART/USB download. |
| D_esd BOM | USBLC6-2SC6 / LESD5D5.0CT1G SOT-23-6 / SOD-523 | ESD surge protection on USB D+/D- — place right next to USB Type-C connector before IO18/IO19/IO20. |
| ESP32-S3-MINI-1-N8 / 1U-N4R2 Espressif | 100% Drop-in | Same 15.4×15.4mm 65-pad footprint as ESP32-S2-MINI-2 — verify USB GPIO 19/20 pin mapping. |
Technical Frequently Asked Questions (FAQ) — ESP32-S3-MINI-1U-N4R2 (SMD,15.4x15.4mm)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of ESP32-S3-MINI-1U-N4R2 (SMD,15.4x15.4mm)?
Manufactured by ESPRESSIF, the ESP32-S3-MINI-1U-N4R2 is housed in a SMD,15.4x15.4mm package with 65 pins and a 0.85 mm lead pitch, supporting a VCC supply range of 3.0 ~ 3.6 V. Key pins include: 1 (GND: Ground Reference Pin (GND)), 2 (GND: Ground Reference Pin (GND)), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (NC: No Connect (Leave Floating)), 5 (IO2: GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1), 6 (IO3: GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)).
What are the IPC-7351B PCB Footprint dimensions for ESP32-S3-MINI-1U-N4R2?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ESP32-S3-MINI-1U-N4R2 (SMD,15.4x15.4mm) has a nominal body envelope of 15.40 × 15.40 mm, pitch e = 0.85 mm, and 73 copper pads plus a central exposed thermal pad (EPAD) of 4.50 × 4.50 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ESP32-S3-MINI-1U-N4R2?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ESP32-S3-MINI-1U-N4R2 (ESPRESSIF, SMD,15.4x15.4mm) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (65 pins) & ESP32-S3-MINI Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 2 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 3 | 3V3 | Power_In | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | NC | No_Connect | No Connect (Leave Floating) |
| 5 | IO2 | Digital_IO | GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1 |
| 6 | IO3 | Digital_IO | GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap) |
| 7 | NC | No_Connect | No Connect (Leave Floating) |
| 8 | IO0 | Digital_IO | GPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin) |
| 9 | IO4 | Digital_IO | GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3 |
| 10 | IO5 | Digital_IO | GPIO5 / RTC_GPIO5 / TOUCH5 / ADC1_CH4 |
| 11 | IO6 | Digital_IO | GPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5 |
| 12 | IO7 | Digital_IO | GPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6 |
| 13 | IO15 | Digital_IO | GPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P |
| 14 | IO16 | Digital_IO | GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N |
| 15 | IO17 | Digital_IO | GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6 |
| 16 | IO18 | Digital_IO | GPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3 |
| 17 | IO8 | Digital_IO | GPIO8 / RTC_GPIO8 / TOUCH8 / ADC1_CH7 / SUBSPICS1 |
| 18 | IO19 | Digital_IO | GPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8 |
| 19 | IO20 | Digital_IO | GPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9 |
| 20 | IO9 | Digital_IO | GPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD |
| 21 | IO10 | Digital_IO | GPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0 |
| 22 | IO11 | Digital_IO | GPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID |
| 23 | IO12 | Digital_IO | GPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK |
| 24 | IO13 | Digital_IO | GPIO13 / RTC_GPIO13 / TOUCH13 / ADC2_CH2 / FSPIQ |
| 25 | IO14 | Digital_IO | GPIO14 / RTC_GPIO14 / TOUCH14 / ADC2_CH3 / FSPIWP |
| 26 | IO21 | Digital_IO | GPIO21 / RTC_GPIO21 |
| 27 | IO47 | Digital_IO | GPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF |
| 28 | IO33 | Digital_IO | GPIO33 / FSPIHD / SUBSPIHD / SPIIO4 |
| 29 | IO34 | Digital_IO | Signal terminal IO34 (I, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIIO5, GPIO34, FSPICS0, SUBSPICS0. Supported peripheral buses: SPI. |
| 30 | IO48 | Digital_IO | Signal terminal IO48 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPICLK. Supported peripheral buses: SPI. |
| 31 | IO35 | Digital_IO | Signal terminal IO35 (I, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIIO6, GPIO35, FSPID, SUBSPID. Supported peripheral buses: SPI. |
| 32 | IO36 | Digital_IO | Signal terminal IO36 (I, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIIO7, GPIO36, FSPICLK, SUBSPICLK. Supported peripheral buses: SPI. |
| 33 | IO37 | Digital_IO | Signal terminal IO37 (I, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SPIDQS, GPIO37, FSPIQ, SUBSPIQ. Supported peripheral buses: SPI. |
| 34 | IO38 | Digital_IO | Signal terminal IO38 (I, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO38, FSPIWP, SUBSPIWP. Supported peripheral buses: SPI. |
| 35 | IO39 | Digital_IO | Signal terminal IO39 (I, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTCK, GPIO39, CLK_OUT3, SUBSPICS1. Supported peripheral buses: SPI, SWD/JTAG. |
| 36 | IO40 | Digital_IO | Signal terminal IO40 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTDO, GPIO40, CLK_OUT2. Supported peripheral buses: SWD/JTAG. |
| 37 | IO41 | Digital_IO | Signal terminal IO41 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTDI, GPIO41, CLK_OUT1. Supported peripheral buses: SWD/JTAG. |
| 38 | IO42 | Digital_IO | Signal terminal IO42 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTMS, GPIO42. Supported peripheral buses: SWD/JTAG. |
| 39 | TXD0 | Digital_IO | Signal terminal TXD0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: U0TXD, GPIO43, CLK_OUT1. Supported peripheral buses: UART. |
| 40 | RXD0 | Digital_IO | Signal terminal RXD0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: U0RXD, GPIO44, CLK_OUT2. Supported peripheral buses: UART. |
| 41 | IO45 | Digital_IO | Signal terminal IO45 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO45. Supported peripheral buses: General. |
| 42 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 43 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 44 | IO46 | Digital_IO | Signal terminal IO46 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO46. Supported peripheral buses: General. |
| 45 | EN | Digital_IO | Chip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset. |
| 46 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 47 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 48 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 49 | GND | GND | Bottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |
| 50 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 51 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 52 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 53 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 54 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 55 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 56 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 57 | GND | GND | Bottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |
| 58 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 59 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 60 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 61 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 62 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 63 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 64 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |