PIC18F4455-I/ML (QFN-44-EP(8x8)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of PIC18F4455-I/ML (QFN-44-EP(8x8))?

Manufactured by MICROCHIP, the PIC18F4455-I/ML is housed in a QFN-44-EP(8x8) package with 45 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.0V to 5.5V. Key pins include: 1 (RC7/RX/DT/SDO: Multiplexed I/O & Peripheral Pin RC7/RX/DT/SDO (General)), 2 (RD4/SPP4: Multiplexed I/O & Peripheral Pin RD4/SPP4 (General)), 3 (RD5/SPP5/P1B: Multiplexed I/O & Peripheral Pin RD5/SPP5/P1B (General)), 4 (RD6/SPP6/P1C: Multiplexed I/O & Peripheral Pin RD6/SPP6/P1C (General)), 5 (RD7/SPP7/P1D: Multiplexed I/O & Peripheral Pin RD7/SPP7/P1D (General)), 6 (VSS: Ground Reference Pin (VSS)).

Q: What are the IPC-7351B PCB Footprint dimensions for PIC18F4455-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC18F4455-I/ML (QFN-44-EP(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.65 mm, and 45 copper pads plus a central exposed thermal pad (EPAD) of 6.55 × 6.55 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC18F4455-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC18F4455-I/ML (MICROCHIP, QFN-44-EP(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 8.00mm × 8.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (45/45)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	RC7/RX/DT/SDO	I/O	Multiplexed I/O & Peripheral Pin RC7/RX/DT/SDO (General)
2	RD4/SPP4	I/O	Multiplexed I/O & Peripheral Pin RD4/SPP4 (General)
3	RD5/SPP5/P1B	I/O	Multiplexed I/O & Peripheral Pin RD5/SPP5/P1B (General)
4	RD6/SPP6/P1C	I/O	Multiplexed I/O & Peripheral Pin RD6/SPP6/P1C (General)
5	RD7/SPP7/P1D	I/O	Multiplexed I/O & Peripheral Pin RD7/SPP7/P1D (General)
6	VSS	GND	Ground Reference Pin (VSS)
7	Vdd	Power	Power Supply Input (Vdd — 2.0V to 5.5V)
8	Vdd	Power	Power Supply Input (Vdd — 2.0V to 5.5V)
9	IO4	I/O	GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10	RB1/AN10/INT1/SCK/SCL	I/O	Multiplexed I/O & Peripheral Pin RB1/AN10/INT1/SCK/SCL (SPI, I2C)
11	RB2/AN8/INT2/VMO	I/O	Multiplexed I/O & Peripheral Pin RB2/AN8/INT2/VMO (General)
12	RB3/AN9/CCP2/VPO	I/O	Multiplexed I/O & Peripheral Pin RB3/AN9/CCP2/VPO (General)
13	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
14	RB4/AN11/KBI0/CSSPP	I/O	Multiplexed I/O & Peripheral Pin RB4/AN11/KBI0/CSSPP (General)
15	RB5/KBI1/PGM	I/O	Multiplexed I/O & Peripheral Pin RB5/KBI1/PGM (General)
16	RB6/KBI2/PGC	I/O	Multiplexed I/O & Peripheral Pin RB6/KBI2/PGC (General)
17	RB7/KBI3/PGD	I/O	Multiplexed I/O & Peripheral Pin RB7/KBI3/PGD (General)
18	#MCLR/VPP/RE3	I/O	Multiplexed I/O & Peripheral Pin #MCLR/VPP/RE3 (General)
19	RA0/AN0	I/O	Multiplexed I/O & Peripheral Pin RA0/AN0 (General)
20	RA1/AN1	I/O	Multiplexed I/O & Peripheral Pin RA1/AN1 (General)
21	RA2/AN2/VREF-/CVREF	Analog	Multiplexed I/O & Peripheral Pin RA2/AN2/VREF-/CVREF (General)
22	RA3/AN3/VREF+	Analog	Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)
23	RA4/T0CKI/C1OUT/RCV	I/O	Multiplexed I/O & Peripheral Pin RA4/T0CKI/C1OUT/RCV (General)
24	IO13	I/O	GPIO13 / RTC_GPIO13 / TOUCH13 / ADC2_CH2 / FSPIQ
25	RE0/AN5/CK1SPP	I/O	Multiplexed I/O & Peripheral Pin RE0/AN5/CK1SPP (General)
26	RE1/AN6/CK2SPP	I/O	Multiplexed I/O & Peripheral Pin RE1/AN6/CK2SPP (General)
27	RE2/AN7/OESPP	I/O	Multiplexed I/O & Peripheral Pin RE2/AN7/OESPP (General)
28	Vdd	Power	Power Supply Input (Vdd — 2.0V to 5.5V)
29	Vdd	Power	Power Supply Input (Vdd — 2.0V to 5.5V)
30	Vss	GND	Ground Reference Pin (Vss)
31	Vss	GND	Ground Reference Pin (Vss)
32	OSC1/CLKI	I/O	Multiplexed I/O & Peripheral Pin OSC1/CLKI (RTC/CLK)
33	OSC2/CLKO/RA6	I/O	Multiplexed I/O & Peripheral Pin OSC2/CLKO/RA6 (RTC/CLK)
34	RC0/T1OSO/T13CKI	I/O	Multiplexed I/O & Peripheral Pin RC0/T1OSO/T13CKI (General)
35	RC1/T1OSI/CCP2/#UOE	I/O	Multiplexed I/O & Peripheral Pin RC1/T1OSI/CCP2/#UOE (General)
36	RC2/CCP1/P1A	I/O	Multiplexed I/O & Peripheral Pin RC2/CCP1/P1A (General)
37	Vusb	I/O	Multiplexed I/O & Peripheral Pin Vusb (General)
38	RD0/SPP0	I/O	Multiplexed I/O & Peripheral Pin RD0/SPP0 (General)
39	RD1/SPP1	I/O	Multiplexed I/O & Peripheral Pin RD1/SPP1 (General)
40	RD2/SPP2	I/O	Multiplexed I/O & Peripheral Pin RD2/SPP2 (General)
41	RD3/SPP3	I/O	Multiplexed I/O & Peripheral Pin RD3/SPP3 (General)
42	RC4/D-/VM	I/O	Multiplexed I/O & Peripheral Pin RC4/D-/VM (USB)
43	RC5/D+/VP	I/O	Multiplexed I/O & Peripheral Pin RC5/D+/VP (USB)
44	RC6/TX/CK	I/O	Multiplexed I/O & Peripheral Pin RC6/TX/CK (General)
45	EP	GND	Exposed Thermal & Ground Pad (EP)

PIN 1 RC7/RX/DT/SDO

I/O

Multiplexed I/O & Peripheral Pin RC7/RX/DT/SDO (General)

Design note: Signal terminal RC7/RX/DT/SDO (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC7/RX/DT/SDO. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 16 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

PIC18F4455-I/ML (QFN-44-EP(8x8)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

PIC18F4455-I/ML (QFN-44-EP(8x8)) - 2. Standard Pinout (Top View)

True package pinout (45 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

PIC18F4455-I/ML (QFN-44-EP(8x8)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

PIC18F4455-I/ML (QFN-44-EP(8x8)) - 4. Package Dimensions (D×E×A)

QFN-44-EP(8x8) · 8.00×8.00mm · Pitch 0.65mmExpand ›

5. Recommended Land PatternLAND PATTERN

PIC18F4455-I/ML (QFN-44-EP(8x8)) - 5. Recommended Land Pattern

IPC-7351B Footprint (45 Pads)Expand ›

6. Application SchematicSCHEMATIC

PIC18F4455-I/ML (QFN-44-EP(8x8)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (16 figures · Page 1/2)

Showing 1–12 of 16 uncropped original figures for PIC18F4455

P2 · p02_fig011777×1640px

PIC18F4455-I/ML (QFN-44-EP(8x8)) — DS39632E-page ii © 2009 Microchip Technology Inc. | Trademarks | FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology In

DS39632E-page ii © 2009 Microchip Technology Inc. | Trademarks | FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology In

P2 · p02_fig02788×285px

PIC18F4455-I/ML (QFN-44-EP(8x8)) — DS39632E-page ii © 2009 Microchip Technology Inc.

P147 · p147_fig011777×345px

FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM

P147 · p147_fig021777×1073px

FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM

P148 · p148_fig011536×941px

FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM

P171 · p171_fig011778×1042px

17.2.2.3 Internal Pull-up Resistors

P171 · p171_fig021777×983px

FIGURE 17-3: EXTERNAL CIRCUITRY PIC® Microcontroller Host Controller/HUB

P171 · p171_fig02P171

Datasheet Page 171 (p171_fig02)

P188 · p188_fig01867×691px

FIGURE 17-11: SELF-POWER ONLY

P188 · p188_fig021778×1246px

FIGURE 17-10: BUS POWER ONLY

P203 · p203_fig011777×938px

FIGURE 19-2: SPI MASTER/SLAVE CONNECTION

P411 · p411_fig031777×837px

PIC18F4455-I/ML (QFN-44-EP(8x8)) — © 2009 Microchip Technology Inc. DS39632E-page 409 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-spe

© 2009 Microchip Technology Inc. DS39632E-page 409 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-spe

Page 1 / 2 (16 extracted figures)

Technical Specifications & Part Details (PIC18F4455-I/ML)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:PIC18F4455-I/ML (QFN-44-EP(8x8)) is a 44-pin standard electronic & interconnect component featuring a 8.00 × 8.00 × 0.90 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 2.0V to 5.5V supply operation across -10°C to +70°C with integrated USB, UART, SPI, I2C, ADC, PWM, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

2.0V to 5.5V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-10°C to +70°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

32 kHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

8.00 × 8.00 × 0.90 mm (A1=0.03 mm)

Package family: QFN (QFN-44-EP(8x8))

Pin Count & Lead PitchN / e

44 Pins | Pitch e = 0.65 mm (25.6 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

USB, UART, SPI, I2C, ADC, PWM, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol45 auto-grouped pins

IPC-7351B Land Pattern45 pads · Pitch 0.65mm

IPC-7525 60% Solder PasteEPAD 6.55×6.55mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-44-EP(8x8))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

8.00 × 8.00 mm

Height (A) & Pitch (e)IPC-7351B

A=0.90mm · e=0.65mm

Pad Size (W × L)Level B

0.28 × 0.80 mm

Pins / Total PadsTopology

45P / 45Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit QFN-44-EP(8x8)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC18F4455-I/ML (QFN-44-EP(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC18F4455-I/ML (QFN-44-EP(8x8))?

Manufactured by MICROCHIP, the PIC18F4455-I/ML is housed in a QFN-44-EP(8x8) package with 45 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.0V to 5.5V. Key pins include: 1 (RC7/RX/DT/SDO: Multiplexed I/O & Peripheral Pin RC7/RX/DT/SDO (General)), 2 (RD4/SPP4: Multiplexed I/O & Peripheral Pin RD4/SPP4 (General)), 3 (RD5/SPP5/P1B: Multiplexed I/O & Peripheral Pin RD5/SPP5/P1B (General)), 4 (RD6/SPP6/P1C: Multiplexed I/O & Peripheral Pin RD6/SPP6/P1C (General)), 5 (RD7/SPP7/P1D: Multiplexed I/O & Peripheral Pin RD7/SPP7/P1D (General)), 6 (VSS: Ground Reference Pin (VSS)).

What are the IPC-7351B PCB Footprint dimensions for PIC18F4455-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC18F4455-I/ML (QFN-44-EP(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.65 mm, and 45 copper pads plus a central exposed thermal pad (EPAD) of 6.55 × 6.55 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC18F4455-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC18F4455-I/ML (MICROCHIP, QFN-44-EP(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (45 pins) & PIC18F4455 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	RC7/RX/DT/SDO	Digital_IO	Signal terminal RC7/RX/DT/SDO (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC7/RX/DT/SDO. Supported peripheral buses: General.
2	RD4/SPP4	Digital_IO	Signal terminal RD4/SPP4 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD4/SPP4. Supported peripheral buses: General.
3	RD5/SPP5/P1B	Digital_IO	Signal terminal RD5/SPP5/P1B (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD5/SPP5/P1B. Supported peripheral buses: General.
4	RD6/SPP6/P1C	Digital_IO	Signal terminal RD6/SPP6/P1C (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD6/SPP6/P1C. Supported peripheral buses: General.
5	RD7/SPP7/P1D	Digital_IO	Signal terminal RD7/SPP7/P1D (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD7/SPP7/P1D. Supported peripheral buses: General.
6	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
7	Vdd	Power_In	Primary positive power supply input (Vdd) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
8	Vdd	Power_In	Primary positive power supply input (Vdd) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
9	IO4	Digital_IO	GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10	RB1/AN10/INT1/SCK/SCL	Digital_IO	Signal terminal RB1/AN10/INT1/SCK/SCL (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB1/AN10/INT1/SCK/SCL. Supported peripheral buses: SPI, I2C.
11	RB2/AN8/INT2/VMO	Digital_IO	Signal terminal RB2/AN8/INT2/VMO (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB2/AN8/INT2/VMO. Supported peripheral buses: General.
12	RB3/AN9/CCP2/VPO	Digital_IO	Signal terminal RB3/AN9/CCP2/VPO (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB3/AN9/CCP2/VPO. Supported peripheral buses: General.
13	NC	NC	Signal terminal NC (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
14	RB4/AN11/KBI0/CSSPP	Digital_IO	Signal terminal RB4/AN11/KBI0/CSSPP (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB4/AN11/KBI0/CSSPP. Supported peripheral buses: General.
15	RB5/KBI1/PGM	Digital_IO	Signal terminal RB5/KBI1/PGM (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB5/KBI1/PGM. Supported peripheral buses: General.
16	RB6/KBI2/PGC	Digital_IO	Signal terminal RB6/KBI2/PGC (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB6/KBI2/PGC. Supported peripheral buses: General.
17	RB7/KBI3/PGD	Digital_IO	Signal terminal RB7/KBI3/PGD (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB7/KBI3/PGD. Supported peripheral buses: General.
18	#MCLR/VPP/RE3	Digital_IO	Signal terminal #MCLR/VPP/RE3 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: #MCLR/VPP/RE3. Supported peripheral buses: General.
19	RA0/AN0	Digital_IO	Signal terminal RA0/AN0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA0/AN0. Supported peripheral buses: General.
20	RA1/AN1	Digital_IO	Signal terminal RA1/AN1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA1/AN1. Supported peripheral buses: General.
21	RA2/AN2/VREF-/CVREF	Analog	Signal terminal RA2/AN2/VREF-/CVREF (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA2/AN2/VREF-/CVREF. Supported peripheral buses: General.
22	RA3/AN3/VREF+	Analog	Signal terminal RA3/AN3/VREF+ (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA3/AN3/VREF+. Supported peripheral buses: General.
23	RA4/T0CKI/C1OUT/RCV	Digital_IO	Signal terminal RA4/T0CKI/C1OUT/RCV (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA4/T0CKI/C1OUT/RCV. Supported peripheral buses: General.
24	IO13	Digital_IO	GPIO13 / RTC_GPIO13 / TOUCH13 / ADC2_CH2 / FSPIQ
25	RE0/AN5/CK1SPP	Digital_IO	Signal terminal RE0/AN5/CK1SPP (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RE0/AN5/CK1SPP. Supported peripheral buses: General.
26	RE1/AN6/CK2SPP	Digital_IO	Signal terminal RE1/AN6/CK2SPP (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RE1/AN6/CK2SPP. Supported peripheral buses: General.
27	RE2/AN7/OESPP	Digital_IO	Signal terminal RE2/AN7/OESPP (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RE2/AN7/OESPP. Supported peripheral buses: General.
28	Vdd	Power_In	Primary positive power supply input (Vdd) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
29	Vdd	Power_In	Primary positive power supply input (Vdd) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
30	Vss	GND	0V electrical ground return terminal (Vss) for internal core logic, I/O drivers, and analog sub-blocks.
31	Vss	GND	0V electrical ground return terminal (Vss) for internal core logic, I/O drivers, and analog sub-blocks.
32	OSC1/CLKI	Digital_IO	Signal terminal OSC1/CLKI (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: OSC1/CLKI. Supported peripheral buses: RTC/CLK.
33	OSC2/CLKO/RA6	Digital_IO	Signal terminal OSC2/CLKO/RA6 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: OSC2/CLKO/RA6. Supported peripheral buses: RTC/CLK.
34	RC0/T1OSO/T13CKI	Digital_IO	Signal terminal RC0/T1OSO/T13CKI (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC0/T1OSO/T13CKI. Supported peripheral buses: General.
35	RC1/T1OSI/CCP2/#UOE	Digital_IO	Signal terminal RC1/T1OSI/CCP2/#UOE (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC1/T1OSI/CCP2/#UOE. Supported peripheral buses: General.
36	RC2/CCP1/P1A	Digital_IO	Signal terminal RC2/CCP1/P1A (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC2/CCP1/P1A. Supported peripheral buses: General.
37	Vusb	Digital_IO	Signal terminal Vusb (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: Vusb. Supported peripheral buses: General.
38	RD0/SPP0	Digital_IO	Signal terminal RD0/SPP0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD0/SPP0. Supported peripheral buses: General.
39	RD1/SPP1	Digital_IO	Signal terminal RD1/SPP1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD1/SPP1. Supported peripheral buses: General.
40	RD2/SPP2	Digital_IO	Signal terminal RD2/SPP2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD2/SPP2. Supported peripheral buses: General.
41	RD3/SPP3	Digital_IO	Signal terminal RD3/SPP3 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD3/SPP3. Supported peripheral buses: General.
42	RC4/D-/VM	Digital_IO	Signal terminal RC4/D-/VM (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC4/D-/VM. Supported peripheral buses: USB.
43	RC5/D+/VP	Digital_IO	Signal terminal RC5/D+/VP (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC5/D+/VP. Supported peripheral buses: USB.
44	RC6/TX/CK	Digital_IO	Signal terminal RC6/TX/CK (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC6/TX/CK. Supported peripheral buses: General.
45	EP	GND	Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.

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