PIC18F44K22-I/ML (QFN-44-EP(8x8)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of PIC18F44K22-I/ML (QFN-44-EP(8x8))?

Manufactured by MICROCHIP, the PIC18F44K22-I/ML is housed in a QFN-44-EP(8x8) package with 45 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.3V to 5.5V. Key pins include: 1 (RC7: Multiplexed I/O & Peripheral Pin RC7 (General)), 2 (RD4: Multiplexed I/O & Peripheral Pin RD4 (General)), 3 (RD5: Multiplexed I/O & Peripheral Pin RD5 (General)), 4 (RD6: Multiplexed I/O & Peripheral Pin RD6 (General)), 5 (RD7: Multiplexed I/O & Peripheral Pin RD7 (General)), 6 (VSS: Ground Reference Pin (VSS)).

Q: What are the IPC-7351B PCB Footprint dimensions for PIC18F44K22-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC18F44K22-I/ML (QFN-44-EP(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.50 mm, and 45 copper pads plus a central exposed thermal pad (EPAD) of 6.60 × 6.60 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC18F44K22-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC18F44K22-I/ML (MICROCHIP, QFN-44-EP(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 8.00mm × 8.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (45/45)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	RC7	I/O	Multiplexed I/O & Peripheral Pin RC7 (General)
2	RD4	I/O	Multiplexed I/O & Peripheral Pin RD4 (General)
3	RD5	I/O	Multiplexed I/O & Peripheral Pin RD5 (General)
4	RD6	I/O	Multiplexed I/O & Peripheral Pin RD6 (General)
5	RD7	I/O	Multiplexed I/O & Peripheral Pin RD7 (General)
6	VSS	GND	Ground Reference Pin (VSS)
7	VDD	Power	Power Supply Input (VDD — 2.3V to 5.5V)
8	VDD	Power	Power Supply Input (VDD — 2.3V to 5.5V)
9	RB0	I/O	Multiplexed I/O & Peripheral Pin RB0 (General)
10	RB1	I/O	Multiplexed I/O & Peripheral Pin RB1 (General)
11	RB2	I/O	Multiplexed I/O & Peripheral Pin RB2 (General)
12	RB3	I/O	Multiplexed I/O & Peripheral Pin RB3 (General)
13	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
14	RB4	I/O	Multiplexed I/O & Peripheral Pin RB4 (General)
15	RB5	I/O	Multiplexed I/O & Peripheral Pin RB5 (General)
16	PGC/RB6	I/O	Multiplexed I/O & Peripheral Pin PGC/RB6 (General)
17	PGD/RB7	I/O	Multiplexed I/O & Peripheral Pin PGD/RB7 (General)
18	MCLR#/VPP/RE3	I/O	Multiplexed I/O & Peripheral Pin MCLR#/VPP/RE3 (General)
19	RA0	I/O	Multiplexed I/O & Peripheral Pin RA0 (General)
20	RA1	I/O	Multiplexed I/O & Peripheral Pin RA1 (General)
21	RA2	I/O	Multiplexed I/O & Peripheral Pin RA2 (General)
22	RA3	I/O	Multiplexed I/O & Peripheral Pin RA3 (General)
23	RA4	I/O	Multiplexed I/O & Peripheral Pin RA4 (General)
24	RA5	I/O	Multiplexed I/O & Peripheral Pin RA5 (General)
25	RE0	I/O	Multiplexed I/O & Peripheral Pin RE0 (General)
26	RE1	I/O	Multiplexed I/O & Peripheral Pin RE1 (General)
27	RE2	I/O	Multiplexed I/O & Peripheral Pin RE2 (General)
28	VDD	Power	Power Supply Input (VDD — 2.3V to 5.5V)
29	VDD	Power	Power Supply Input (VDD — 2.3V to 5.5V)
30	VSS	GND	Ground Reference Pin (VSS)
31	VSS	GND	Ground Reference Pin (VSS)
32	RA7	I/O	Multiplexed I/O & Peripheral Pin RA7 (General)
33	RA6	I/O	Multiplexed I/O & Peripheral Pin RA6 (General)
34	RC0	I/O	Multiplexed I/O & Peripheral Pin RC0 (General)
35	RC1	I/O	Multiplexed I/O & Peripheral Pin RC1 (General)
36	RC2	I/O	Multiplexed I/O & Peripheral Pin RC2 (General)
37	RC3	I/O	Multiplexed I/O & Peripheral Pin RC3 (General)
38	RD0	I/O	Multiplexed I/O & Peripheral Pin RD0 (General)
39	RD1	I/O	Multiplexed I/O & Peripheral Pin RD1 (General)
40	RD2	I/O	Multiplexed I/O & Peripheral Pin RD2 (General)
41	RD3	I/O	Multiplexed I/O & Peripheral Pin RD3 (General)
42	RC4	I/O	Multiplexed I/O & Peripheral Pin RC4 (General)
43	RC5	I/O	Multiplexed I/O & Peripheral Pin RC5 (General)
44	RC6	I/O	Multiplexed I/O & Peripheral Pin RC6 (General)
45	PAD	I/O	Multiplexed I/O & Peripheral Pin PAD (General)

PIN 1 RC7

I/O

Multiplexed I/O & Peripheral Pin RC7 (General)

Design note: Signal terminal RC7 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RC7. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 16 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

PIC18F44K22-I/ML (QFN-44-EP(8x8)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

PIC18F44K22-I/ML (QFN-44-EP(8x8)) - 2. Standard Pinout (Top View)

True package pinout (45 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

PIC18F44K22-I/ML (QFN-44-EP(8x8)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

PIC18F44K22-I/ML (QFN-44-EP(8x8)) - 4. Package Dimensions (D×E×A)

QFN-44-EP(8x8) · 8.00×8.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

PIC18F44K22-I/ML (QFN-44-EP(8x8)) - 5. Recommended Land Pattern

IPC-7351B Footprint (45 Pads)Expand ›

6. Application SchematicSCHEMATIC

PIC18F44K22-I/ML (QFN-44-EP(8x8)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (16 figures · Page 1/2)

Showing 1–12 of 16 uncropped original figures for PIC18F44K22

P1 · p01_fig01377×200px

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with XLP Technology

P174 · p174_fig01867×587px

FIGURE 14-1: CAPTURE MODE OPERATION BLOCK DIAGRAM

P174 · p174_fig021783×648px

See Section 12.0 “Timer1/3/5 Module with Gate Control” for more information on configuring the 16-bit Timers.

P177 · p177_fig011715×926px

FIGURE 14-2: COMPARE MODE OPERATION BLOCK DIAGRAM

P185 · p185_fig011555×1052px

FIGURE 14-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)

P185 · p185_fig01P185

Datasheet Page 185 (p185_fig01)

P195 · p195_fig011738×564px

FIGURE 14-19: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRxSYNC = 0)

P195 · p195_fig021683×584px

FIGURE 14-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRxSYNC = 1)

P321 · p321_fig01978×657px

FIGURE 19-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT

P322 · p322_fig011422×948px

FIGURE 19-4: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION

P322 · p322_fig01P322

Datasheet Page 322 (p322_fig01)

P529 · p529_fig011778×2500px

PIC18F44K22-I/ML (QFN-44-EP(8x8)) —  2010-2016 Microchip Technology Inc. DS40001412G-page 529 | Microchip Technology Drawing C04-103D Sheet 2 of 2 | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/pa

 2010-2016 Microchip Technology Inc. DS40001412G-page 529 | Microchip Technology Drawing C04-103D Sheet 2 of 2 | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/pa

Page 1 / 2 (16 extracted figures)

Technical Specifications & Part Details (PIC18F44K22-I/ML)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:PIC18F44K22-I/ML (QFN-44-EP(8x8)) is a 44-pin standard electronic & interconnect component featuring a 8.00 × 8.00 × 1.00 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.3V to 5.5V supply operation across -40°C to +125°C with integrated UART, SPI, I2C, ADC, DAC, PWM interfaces.

Operating Supply VoltageV_CC / V_DD

2.3V to 5.5V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to +125°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

16 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

8.00 × 8.00 × 1.00 mm (A1=0.03 mm)

Package family: QFN (QFN-44-EP(8x8))

Pin Count & Lead PitchN / e

44 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

UART, SPI, I2C, ADC, DAC, PWM

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol45 auto-grouped pins

IPC-7351B Land Pattern45 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteEPAD 6.60×6.60mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-44-EP(8x8))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

8.00 × 8.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.00mm · e=0.50mm

Pad Size (W × L)Level B

0.35 × 0.85 mm

Pins / Total PadsTopology

45P / 45Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit QFN-44-EP(8x8)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC18F44K22-I/ML (QFN-44-EP(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC18F44K22-I/ML (QFN-44-EP(8x8))?

Manufactured by MICROCHIP, the PIC18F44K22-I/ML is housed in a QFN-44-EP(8x8) package with 45 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.3V to 5.5V. Key pins include: 1 (RC7: Multiplexed I/O & Peripheral Pin RC7 (General)), 2 (RD4: Multiplexed I/O & Peripheral Pin RD4 (General)), 3 (RD5: Multiplexed I/O & Peripheral Pin RD5 (General)), 4 (RD6: Multiplexed I/O & Peripheral Pin RD6 (General)), 5 (RD7: Multiplexed I/O & Peripheral Pin RD7 (General)), 6 (VSS: Ground Reference Pin (VSS)).

What are the IPC-7351B PCB Footprint dimensions for PIC18F44K22-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC18F44K22-I/ML (QFN-44-EP(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.50 mm, and 45 copper pads plus a central exposed thermal pad (EPAD) of 6.60 × 6.60 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC18F44K22-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC18F44K22-I/ML (MICROCHIP, QFN-44-EP(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (45 pins) & PIC18F44K22 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	RC7	Digital_IO	Signal terminal RC7 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RC7. Supported peripheral buses: General.
2	RD4	Digital_IO	Signal terminal RD4 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RD4. Supported peripheral buses: General.
3	RD5	Digital_IO	Signal terminal RD5 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RD5. Supported peripheral buses: General.
4	RD6	Digital_IO	Signal terminal RD6 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RD6. Supported peripheral buses: General.
5	RD7	Digital_IO	Signal terminal RD7 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RD7. Supported peripheral buses: General.
6	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
7	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.3V to 5.5V domain (Max rating: 5.5V).
8	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.3V to 5.5V domain (Max rating: 5.5V).
9	RB0	Digital_IO	Signal terminal RB0 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RB0. Supported peripheral buses: General.
10	RB1	Digital_IO	Signal terminal RB1 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RB1. Supported peripheral buses: General.
11	RB2	Digital_IO	Signal terminal RB2 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RB2. Supported peripheral buses: General.
12	RB3	Digital_IO	Signal terminal RB3 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RB3. Supported peripheral buses: General.
13	NC	NC	Signal terminal NC (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
14	RB4	Digital_IO	Signal terminal RB4 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RB4. Supported peripheral buses: General.
15	RB5	Digital_IO	Signal terminal RB5 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RB5. Supported peripheral buses: General.
16	PGC/RB6	Digital_IO	Signal terminal PGC/RB6 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: PGC/RB6. Supported peripheral buses: General.
17	PGD/RB7	Digital_IO	Signal terminal PGD/RB7 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: PGD/RB7. Supported peripheral buses: General.
18	MCLR#/VPP/RE3	Digital_IO	Signal terminal MCLR#/VPP/RE3 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: MCLR#/VPP/RE3. Supported peripheral buses: General.
19	RA0	Digital_IO	Signal terminal RA0 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RA0. Supported peripheral buses: General.
20	RA1	Digital_IO	Signal terminal RA1 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RA1. Supported peripheral buses: General.
21	RA2	Digital_IO	Signal terminal RA2 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RA2. Supported peripheral buses: General.
22	RA3	Digital_IO	Signal terminal RA3 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RA3. Supported peripheral buses: General.
23	RA4	Digital_IO	Signal terminal RA4 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RA4. Supported peripheral buses: General.
24	RA5	Digital_IO	Signal terminal RA5 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RA5. Supported peripheral buses: General.
25	RE0	Digital_IO	Signal terminal RE0 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RE0. Supported peripheral buses: General.
26	RE1	Digital_IO	Signal terminal RE1 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RE1. Supported peripheral buses: General.
27	RE2	Digital_IO	Signal terminal RE2 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RE2. Supported peripheral buses: General.
28	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.3V to 5.5V domain (Max rating: 5.5V).
29	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.3V to 5.5V domain (Max rating: 5.5V).
30	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
31	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
32	RA7	Digital_IO	Signal terminal RA7 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RA7. Supported peripheral buses: General.
33	RA6	Digital_IO	Signal terminal RA6 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RA6. Supported peripheral buses: General.
34	RC0	Digital_IO	Signal terminal RC0 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RC0. Supported peripheral buses: General.
35	RC1	Digital_IO	Signal terminal RC1 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RC1. Supported peripheral buses: General.
36	RC2	Digital_IO	Signal terminal RC2 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RC2. Supported peripheral buses: General.
37	RC3	Digital_IO	Signal terminal RC3 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RC3. Supported peripheral buses: General.
38	RD0	Digital_IO	Signal terminal RD0 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RD0. Supported peripheral buses: General.
39	RD1	Digital_IO	Signal terminal RD1 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RD1. Supported peripheral buses: General.
40	RD2	Digital_IO	Signal terminal RD2 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RD2. Supported peripheral buses: General.
41	RD3	Digital_IO	Signal terminal RD3 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RD3. Supported peripheral buses: General.
42	RC4	Digital_IO	Signal terminal RC4 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RC4. Supported peripheral buses: General.
43	RC5	Digital_IO	Signal terminal RC5 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RC5. Supported peripheral buses: General.
44	RC6	Digital_IO	Signal terminal RC6 (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: RC6. Supported peripheral buses: General.
45	PAD	Digital_IO	Signal terminal PAD (I/O, 2.3V to 5.5V domain). Multiplexed alternate functions: PAD. Supported peripheral buses: General.

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