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MTCH6301-I/ML (QFN-44-EP(8x8)) — Symbol, Footprint IPC-7351B & 3D STEP Model

MTCH6301-I/ML

MICROCHIPID: C219572QFN-44-EP(8x8) · 45 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · MTCH6301-I/ML (QFN-44-EP(8x8))1SDA2TX173TX164TX155TX146VSS7VCAP8INT9N/C10RX1211RX1112TX1313TX1214RX1015RX916VSS17VDD18RESET19RX820RX721RX622RX523RX445EPAD44SCL43TX1142TX1041TX940VDD39VSS38TX537TX636TX735TX834TX433TX032TX131TX230TX329VSS28VDD27RX026RX125RX224RX3Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.835.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445E=8.00mm · Pitch e=0.65mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (45/45)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1SDAI/OMultiplexed I/O & Peripheral Pin SDA (I2C)
2TX17I/OMultiplexed I/O & Peripheral Pin TX17 (General)
3TX16I/OMultiplexed I/O & Peripheral Pin TX16 (General)
4TX15I/OMultiplexed I/O & Peripheral Pin TX15 (General)
5TX14I/OMultiplexed I/O & Peripheral Pin TX14 (General)
6VSSGNDGround Reference Pin (VSS)
7VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
8INTI/OMultiplexed I/O & Peripheral Pin INT (General)
9N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
10RX12I/OMultiplexed I/O & Peripheral Pin RX12 (General)
11RX11I/OMultiplexed I/O & Peripheral Pin RX11 (General)
12TX13I/OMultiplexed I/O & Peripheral Pin TX13 (General)
13TX12I/OMultiplexed I/O & Peripheral Pin TX12 (General)
14RX10I/OMultiplexed I/O & Peripheral Pin RX10 (General)
15RX9I/OMultiplexed I/O & Peripheral Pin RX9 (General)
16VSSGNDGround Reference Pin (VSS)
17VDDPowerPower Supply Input (VDD — 2.4V to 3.6V)
18RESETISystem Enable & Hardware Reset (RESET)
19RX8I/OMultiplexed I/O & Peripheral Pin RX8 (General)
20RX7I/OMultiplexed I/O & Peripheral Pin RX7 (General)
21RX6I/OMultiplexed I/O & Peripheral Pin RX6 (General)
22RX5I/OMultiplexed I/O & Peripheral Pin RX5 (General)
23RX4I/OMultiplexed I/O & Peripheral Pin RX4 (General)
24RX3I/OMultiplexed I/O & Peripheral Pin RX3 (General)
25RX2I/OMultiplexed I/O & Peripheral Pin RX2 (General)
26RX1I/OMultiplexed I/O & Peripheral Pin RX1 (General)
27RX0I/OMultiplexed I/O & Peripheral Pin RX0 (General)
28VDDPowerPower Supply Input (VDD — 2.4V to 3.6V)
29VSSGNDGround Reference Pin (VSS)
30TX3I/OMultiplexed I/O & Peripheral Pin TX3 (General)
31TX2I/OMultiplexed I/O & Peripheral Pin TX2 (General)
32TX1I/OMultiplexed I/O & Peripheral Pin TX1 (General)
33TX0I/OMultiplexed I/O & Peripheral Pin TX0 (UART)
34TX4I/OMultiplexed I/O & Peripheral Pin TX4 (General)
35TX8I/OMultiplexed I/O & Peripheral Pin TX8 (General)
36TX7I/OMultiplexed I/O & Peripheral Pin TX7 (General)
37TX6I/OMultiplexed I/O & Peripheral Pin TX6 (General)
38TX5I/OMultiplexed I/O & Peripheral Pin TX5 (General)
39VSSGNDExposed Thermal & Ground Pad (VSS)
40VDDPowerPower Supply Input (VDD — 2.4V to 3.6V)
41TX9I/OMultiplexed I/O & Peripheral Pin TX9 (General)
42TX10I/OMultiplexed I/O & Peripheral Pin TX10 (General)
43TX11I/OMultiplexed I/O & Peripheral Pin TX11 (General)
44SCLI/OMultiplexed I/O & Peripheral Pin SCL (I2C)
45EPADGNDExposed Thermal & Ground Pad (EPAD)
PIN 1 SDA
I/O
Multiplexed I/O & Peripheral Pin SDA (I2C)
Design note: SynchronousSerialDataInput/OutputforI2C™
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: MTCH6301-I/ML (MICROCHIP · QFN-44-EP(8x8))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
MTCH6301-I/ML (QFN-44-EP(8x8)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
MTCH6301-I/ML (QFN-44-EP(8x8)) - 2. Standard Pinout (Top View)
True package pinout (45 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
MTCH6301-I/ML (QFN-44-EP(8x8)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
MTCH6301-I/ML (QFN-44-EP(8x8)) - 4. Package Dimensions (D×E×A)
QFN-44-EP(8x8) · 8.00×8.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
MTCH6301-I/ML (QFN-44-EP(8x8)) - 5. Recommended Land Pattern
IPC-7351B Footprint (45 Pads)Expand ›
6. Application SchematicSCHEMATIC
MTCH6301-I/ML (QFN-44-EP(8x8)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for MTCH6301
P1 · p01_fig01376×200px
MTCH6301-I/ML (QFN-44-EP(8x8)) — MTCH6301 Projected Capacitive Touch Controller
MTCH6301 Projected Capacitive Touch Controller
P3 · p03_fig011777×1368px
MTCH6301-I/ML (QFN-44-EP(8x8)) — FIGURE 1-1: SYSTEM BLOCK DIAGRAM
FIGURE 1-1: SYSTEM BLOCK DIAGRAM
P4 · p04_fig011257×1285px
MTCH6301-I/ML (QFN-44-EP(8x8)) — FIGURE 3-1: 44-PIN TQFP, QFN(1,2)
FIGURE 3-1: 44-PIN TQFP, QFN(1,2)
P4 · p04_fig01P4
MTCH6301-I/ML (QFN-44-EP(8x8)) — Datasheet Page 4 (p04_fig01)
Datasheet Page 4 (p04_fig01)
P6 · p06_fig011777×1239px
MTCH6301-I/ML (QFN-44-EP(8x8)) — FIGURE 5-1: TYPICAL APPLICATION CIRCUIT MICROCHIP PICkitTM Serial Analyzer
FIGURE 5-1: TYPICAL APPLICATION CIRCUIT MICROCHIP PICkitTM Serial Analyzer
P11 · p11_fig011777×1302px
MTCH6301-I/ML (QFN-44-EP(8x8)) — FIGURE 5-3: CUSTOM APPLICATION LAYOUT
FIGURE 5-3: CUSTOM APPLICATION LAYOUT
P11 · p11_fig01P11
MTCH6301-I/ML (QFN-44-EP(8x8)) — Datasheet Page 11 (p11_fig01)
Datasheet Page 11 (p11_fig01)
P31 · p31_fig011712×1201px
MTCH6301-I/ML (QFN-44-EP(8x8)) — 44-Lead QFN (8x8x0.9 mm) Example
44-Lead QFN (8x8x0.9 mm) Example
P31 · p31_fig021777×831px
MTCH6301-I/ML (QFN-44-EP(8x8)) —  2012-2014 Microchip Technology Inc. DS40001663B-page 31 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for custo
 2012-2014 Microchip Technology Inc. DS40001663B-page 31 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for custo
P31 · p31_fig01P31
MTCH6301-I/ML (QFN-44-EP(8x8)) — Datasheet Page 31 (p31_fig01)
Datasheet Page 31 (p31_fig01)

Technical Specifications & Part Details (MTCH6301-I/ML)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:MTCH6301-I/ML (QFN-44-EP(8x8)) is a 44-pin standard electronic & interconnect component featuring a 8.00 × 8.00 × 0.90 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 2.4V to 3.6V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, I2C, ADC, UART interfaces.
Operating Supply VoltageV_CC / V_DD
2.4V to 3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-44-EP(8x8))
Pin Count & Lead PitchN / e
44 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, I2C, ADC, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol45 auto-grouped pins
OK
IPC-7351B Land Pattern45 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteEPAD 6.55×6.55mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-44-EP(8x8))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.65mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
45P / 45Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-44-EP(8x8)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MTCH6301-I/ML (QFN-44-EP(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MTCH6301-I/ML (QFN-44-EP(8x8))?

Manufactured by MICROCHIP, the MTCH6301-I/ML is housed in a QFN-44-EP(8x8) package with 45 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.4V to 3.6V. Key pins include: 1 (SDA: Multiplexed I/O & Peripheral Pin SDA (I2C)), 2 (TX17: Multiplexed I/O & Peripheral Pin TX17 (General)), 3 (TX16: Multiplexed I/O & Peripheral Pin TX16 (General)), 4 (TX15: Multiplexed I/O & Peripheral Pin TX15 (General)), 5 (TX14: Multiplexed I/O & Peripheral Pin TX14 (General)), 6 (VSS: Ground Reference Pin (VSS)).

What are the IPC-7351B PCB Footprint dimensions for MTCH6301-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MTCH6301-I/ML (QFN-44-EP(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.65 mm, and 45 copper pads plus a central exposed thermal pad (EPAD) of 6.55 × 6.55 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MTCH6301-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MTCH6301-I/ML (MICROCHIP, QFN-44-EP(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (45 pins) & MTCH6301 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1SDADigital_IOSignal terminal SDA (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
2TX17Digital_IOSignal terminal TX17 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: TX17. Supported peripheral buses: General.
3TX16Digital_IOSignal terminal TX16 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: TX16. Supported peripheral buses: General.
4TX15Digital_IOSignal terminal TX15 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: TX15. Supported peripheral buses: General.
5TX14Digital_IOSignal terminal TX14 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: TX14. Supported peripheral buses: General.
6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
7VCAPDigital_IOSignal terminal VCAP (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
8INTDigital_IOSignal terminal INT (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: INT. Supported peripheral buses: General.
9N/CDigital_IOSignal terminal N/C (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
10RX12Digital_IOSignal terminal RX12 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: RX12. Supported peripheral buses: General.
11RX11Digital_IOSignal terminal RX11 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: RX11. Supported peripheral buses: General.
12TX13Digital_IOSignal terminal TX13 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: TX13. Supported peripheral buses: General.
13TX12Digital_IOSignal terminal TX12 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: TX12. Supported peripheral buses: General.
14RX10Digital_IOSignal terminal RX10 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: RX10. Supported peripheral buses: General.
15RX9Digital_IOSignal terminal RX9 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: RX9. Supported peripheral buses: General.
16VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
17VDDPower_InPrimary positive power supply input (VDD) operating in the 2.4V to 3.6V domain (Max rating: 3.6V).
18RESETDigital_IOActive-low hardware reset terminal (RESET): pulling this pin Low resets the processor core and peripherals.
19RX8Digital_IOSignal terminal RX8 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: RX8. Supported peripheral buses: General.
20RX7Digital_IOSignal terminal RX7 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: RX7. Supported peripheral buses: General.
21RX6Digital_IOSignal terminal RX6 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: RX6. Supported peripheral buses: General.
22RX5Digital_IOSignal terminal RX5 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: RX5. Supported peripheral buses: General.
23RX4Digital_IOSignal terminal RX4 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: RX4. Supported peripheral buses: General.
24RX3Digital_IOSignal terminal RX3 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: RX3. Supported peripheral buses: General.
25RX2Digital_IOSignal terminal RX2 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: RX2. Supported peripheral buses: General.
26RX1Digital_IOSignal terminal RX1 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: RX1. Supported peripheral buses: General.
27RX0Digital_IOSignal terminal RX0 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: RX0. Supported peripheral buses: General.
28VDDPower_InPrimary positive power supply input (VDD) operating in the 2.4V to 3.6V domain (Max rating: 3.6V).
29VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
30TX3Digital_IOSignal terminal TX3 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: TX3. Supported peripheral buses: General.
31TX2Digital_IOSignal terminal TX2 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: TX2. Supported peripheral buses: General.
32TX1Digital_IOSignal terminal TX1 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: TX1. Supported peripheral buses: General.
33TX0Digital_IOSignal terminal TX0 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: TX0. Supported peripheral buses: UART.
34TX4Digital_IOSignal terminal TX4 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: TX4. Supported peripheral buses: General.
35TX8Digital_IOSignal terminal TX8 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: TX8. Supported peripheral buses: General.
36TX7Digital_IOSignal terminal TX7 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: TX7. Supported peripheral buses: General.
37TX6Digital_IOSignal terminal TX6 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: TX6. Supported peripheral buses: General.
38TX5Digital_IOSignal terminal TX5 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: TX5. Supported peripheral buses: General.
39VSSGNDBottom exposed die attach pad (VSS) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
40VDDPower_InPrimary positive power supply input (VDD) operating in the 2.4V to 3.6V domain (Max rating: 3.6V).
41TX9Digital_IOSignal terminal TX9 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: TX9. Supported peripheral buses: General.
42TX10Digital_IOSignal terminal TX10 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: TX10. Supported peripheral buses: General.
43TX11Digital_IOSignal terminal TX11 (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: TX11. Supported peripheral buses: General.
44SCLDigital_IOSignal terminal SCL (I/O, 2.4V to 3.6V domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
45EPADGNDBottom exposed die attach pad (EPAD) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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