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PIC18F2450-I/ML (QFN-28-EP(6x6)) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC18F2450-I/ML

MICROCHIPID: C219557QFN-28-EP(6x6) · 29 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC18F2450-I/ML (QFN-28-EP(6x6))1RA2/AN2/VREF2RA3/AN3/VREF3RA4/T0CKI/RC4RA5/AN4/HLVD5VSS6OSC1/CLKI7OSC2/CLKO/RA8RC0/T1OSO/T19RC1/T1OSI/UO10RC2/CCP111VUSB12RC4/D-/VM13RC5/D+/VP14RC6/TX/CK15RC7/RX/DT29EP28RA1/AN127RA0/AN026MCLR#/VPP/RE25RB7/KBI3/PGD24RB6/KBI2/PGC23RB5/KBI1/PGM22RB4/AN11/KBI21RB3/AN9/VPO20RB2/AN8/INT219RB1/AN10/INT18RB0/AN12/INT17VDD16VSSGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.825.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829E=6.00mm · Pitch e=0.65mmD=6.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 6.00mm × 6.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RA2/AN2/VREF-AnalogMultiplexed I/O & Peripheral Pin RA2/AN2/VREF- (General)
2RA3/AN3/VREF+AnalogMultiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)
3RA4/T0CKI/RCVI/OMultiplexed I/O & Peripheral Pin RA4/T0CKI/RCV (General)
4RA5/AN4/HLVDINI/OMultiplexed I/O & Peripheral Pin RA5/AN4/HLVDIN (General)
5VSSGNDGround Reference Pin (VSS)
6OSC1/CLKII/OMultiplexed I/O & Peripheral Pin OSC1/CLKI (RTC/CLK)
7OSC2/CLKO/RA6I/OMultiplexed I/O & Peripheral Pin OSC2/CLKO/RA6 (RTC/CLK)
8RC0/T1OSO/T1CKII/OMultiplexed I/O & Peripheral Pin RC0/T1OSO/T1CKI (General)
9RC1/T1OSI/UOE#I/OMultiplexed I/O & Peripheral Pin RC1/T1OSI/UOE# (General)
10RC2/CCP1I/OMultiplexed I/O & Peripheral Pin RC2/CCP1 (General)
11VUSBI/OMultiplexed I/O & Peripheral Pin VUSB (General)
12RC4/D-/VMI/OMultiplexed I/O & Peripheral Pin RC4/D-/VM (USB)
13RC5/D+/VPI/OMultiplexed I/O & Peripheral Pin RC5/D+/VP (USB)
14RC6/TX/CKI/OMultiplexed I/O & Peripheral Pin RC6/TX/CK (General)
15RC7/RX/DTI/OMultiplexed I/O & Peripheral Pin RC7/RX/DT (General)
16VSSGNDGround Reference Pin (VSS)
17VDDPowerPower Supply Input (VDD — 2.0V to 5.5V)
18RB0/AN12/INT0I/OMultiplexed I/O & Peripheral Pin RB0/AN12/INT0 (General)
19RB1/AN10/INT1I/OMultiplexed I/O & Peripheral Pin RB1/AN10/INT1 (General)
20RB2/AN8/INT2/VMOI/OMultiplexed I/O & Peripheral Pin RB2/AN8/INT2/VMO (General)
21RB3/AN9/VPOI/OMultiplexed I/O & Peripheral Pin RB3/AN9/VPO (General)
22RB4/AN11/KBI0I/OMultiplexed I/O & Peripheral Pin RB4/AN11/KBI0 (General)
23RB5/KBI1/PGMI/OMultiplexed I/O & Peripheral Pin RB5/KBI1/PGM (General)
24RB6/KBI2/PGCI/OMultiplexed I/O & Peripheral Pin RB6/KBI2/PGC (General)
25RB7/KBI3/PGDI/OMultiplexed I/O & Peripheral Pin RB7/KBI3/PGD (General)
26MCLR#/VPP/RE3I/OMultiplexed I/O & Peripheral Pin MCLR#/VPP/RE3 (General)
27RA0/AN0I/OMultiplexed I/O & Peripheral Pin RA0/AN0 (General)
28RA1/AN1I/OMultiplexed I/O & Peripheral Pin RA1/AN1 (General)
29EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 RA2/AN2/VREF-
Analog
Multiplexed I/O & Peripheral Pin RA2/AN2/VREF- (General)
Design note: Signal terminal RA2/AN2/VREF- (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA2/AN2/VREF-. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC18F2450-I/ML (MICROCHIP · QFN-28-EP(6x6))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC18F2450-I/ML (QFN-28-EP(6x6)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC18F2450-I/ML (QFN-28-EP(6x6)) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC18F2450-I/ML (QFN-28-EP(6x6)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC18F2450-I/ML (QFN-28-EP(6x6)) - 4. Package Dimensions (D×E×A)
QFN-28-EP(6x6) · 6.00×6.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC18F2450-I/ML (QFN-28-EP(6x6)) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC18F2450-I/ML (QFN-28-EP(6x6)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for PIC18F2450
P2 · p02_fig011777×1640px
PIC18F2450-I/ML (QFN-28-EP(6x6)) — DS39760D-page ii © 2008 Microchip Technology Inc. | Trademarks | FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporate
DS39760D-page ii © 2008 Microchip Technology Inc. | Trademarks | FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporate
P2 · p02_fig02783×283px
PIC18F2450-I/ML (QFN-28-EP(6x6)) — DS39760D-page ii © 2008 Microchip Technology Inc.
DS39760D-page ii © 2008 Microchip Technology Inc.
P126 · p126_fig011472×382px
PIC18F2450-I/ML (QFN-28-EP(6x6)) — 13.2 Capture Mode
13.2 Capture Mode
P126 · p126_fig021398×457px
PIC18F2450-I/ML (QFN-28-EP(6x6)) — FIGURE 13-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
FIGURE 13-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
P127 · p127_fig011349×482px
PIC18F2450-I/ML (QFN-28-EP(6x6)) — FIGURE 13-2: COMPARE MODE OPERATION BLOCK DIAGRAM
FIGURE 13-2: COMPARE MODE OPERATION BLOCK DIAGRAM
P135 · p135_fig011778×1006px
PIC18F2450-I/ML (QFN-28-EP(6x6)) — 14.2.2.3 Internal Pull-up Resistors
14.2.2.3 Internal Pull-up Resistors
P135 · p135_fig021778×710px
PIC18F2450-I/ML (QFN-28-EP(6x6)) — FIGURE 14-3: EXTERNAL CIRCUITRY PIC® Microcontroller Host Controller/HUB
FIGURE 14-3: EXTERNAL CIRCUITRY PIC® Microcontroller Host Controller/HUB
P135 · p135_fig02P135
PIC18F2450-I/ML (QFN-28-EP(6x6)) — Datasheet Page 135 (p135_fig02)
Datasheet Page 135 (p135_fig02)
P213 · p213_fig011780×599px
PIC18F2450-I/ML (QFN-28-EP(6x6)) — TABLE 18-4: DEBUGGER RESOURCES | TABLE 18-5: EQUIVALENT PINS FOR LEGACY AND DEDICATED ICD/ICSP™ PORTS | I/O pins: RB6, RB7 | Stack: 2 levels | Program Memory: 512 bytes | Data Memory: 10 bytes | Pin Name | Pin Type Pin Function Legacy | Por
TABLE 18-4: DEBUGGER RESOURCES | TABLE 18-5: EQUIVALENT PINS FOR LEGACY AND DEDICATED ICD/ICSP™ PORTS | I/O pins: RB6, RB7 | Stack: 2 levels | Program Memory: 512 bytes | Data Memory: 10 bytes | Pin Name | Pin Type Pin Function Legacy | Por
P214 · p214_fig011779×1137px
PIC18F2450-I/ML (QFN-28-EP(6x6)) — PIC18F2450/4450 | Even when the dedicated port is enabled, the ICSP and ICD functions remain available through the legacy port. When VIHH is seen on the MCLR/VPP/RE3 pin, the state of the ICRST/ICVPP pin is ignored. | 18.9.2 28-PIN EMULATIO
PIC18F2450/4450 | Even when the dedicated port is enabled, the ICSP and ICD functions remain available through the legacy port. When VIHH is seen on the MCLR/VPP/RE3 pin, the state of the ICRST/ICVPP pin is ignored. | 18.9.2 28-PIN EMULATIO
P214 · p214_fig01P214
PIC18F2450-I/ML (QFN-28-EP(6x6)) — Datasheet Page 214 (p214_fig01)
Datasheet Page 214 (p214_fig01)
P297 · p297_fig021777×853px
PIC18F2450-I/ML (QFN-28-EP(6x6)) — © 2008 Microchip Technology Inc. DS39760D-page 295 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-spe
© 2008 Microchip Technology Inc. DS39760D-page 295 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-spe
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (PIC18F2450-I/ML)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC18F2450-I/ML (QFN-28-EP(6x6)) is a 28-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 2.0V to 5.5V supply operation across -10°C to +70°C with integrated USB, UART, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
2.0V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-10°C to +70°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 6.00 × 1.00 mm (A1=0.03 mm)
Package family: QFN (QFN-28-EP(6x6))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteEPAD 4.70×4.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-28-EP(6x6))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.65mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-28-EP(6x6)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC18F2450-I/ML (QFN-28-EP(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC18F2450-I/ML (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the PIC18F2450-I/ML is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.0V to 5.5V. Key pins include: 1 (RA2/AN2/VREF-: Multiplexed I/O & Peripheral Pin RA2/AN2/VREF- (General)), 2 (RA3/AN3/VREF+: Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)), 3 (RA4/T0CKI/RCV: Multiplexed I/O & Peripheral Pin RA4/T0CKI/RCV (General)), 4 (RA5/AN4/HLVDIN: Multiplexed I/O & Peripheral Pin RA5/AN4/HLVDIN (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (OSC1/CLKI: Multiplexed I/O & Peripheral Pin OSC1/CLKI (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for PIC18F2450-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC18F2450-I/ML (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC18F2450-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC18F2450-I/ML (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & PIC18F2450 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RA2/AN2/VREF-AnalogSignal terminal RA2/AN2/VREF- (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA2/AN2/VREF-. Supported peripheral buses: General.
2RA3/AN3/VREF+AnalogSignal terminal RA3/AN3/VREF+ (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA3/AN3/VREF+. Supported peripheral buses: General.
3RA4/T0CKI/RCVDigital_IOSignal terminal RA4/T0CKI/RCV (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA4/T0CKI/RCV. Supported peripheral buses: General.
4RA5/AN4/HLVDINDigital_IOSignal terminal RA5/AN4/HLVDIN (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA5/AN4/HLVDIN. Supported peripheral buses: General.
5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
6OSC1/CLKIDigital_IOSignal terminal OSC1/CLKI (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: OSC1/CLKI. Supported peripheral buses: RTC/CLK.
7OSC2/CLKO/RA6Digital_IOSignal terminal OSC2/CLKO/RA6 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: OSC2/CLKO/RA6. Supported peripheral buses: RTC/CLK.
8RC0/T1OSO/T1CKIDigital_IOSignal terminal RC0/T1OSO/T1CKI (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC0/T1OSO/T1CKI. Supported peripheral buses: General.
9RC1/T1OSI/UOE#Digital_IOSignal terminal RC1/T1OSI/UOE# (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC1/T1OSI/UOE#. Supported peripheral buses: General.
10RC2/CCP1Digital_IOSignal terminal RC2/CCP1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC2/CCP1. Supported peripheral buses: General.
11VUSBDigital_IOSignal terminal VUSB (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: VUSB. Supported peripheral buses: General.
12RC4/D-/VMDigital_IOSignal terminal RC4/D-/VM (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC4/D-/VM. Supported peripheral buses: USB.
13RC5/D+/VPDigital_IOSignal terminal RC5/D+/VP (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC5/D+/VP. Supported peripheral buses: USB.
14RC6/TX/CKDigital_IOSignal terminal RC6/TX/CK (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC6/TX/CK. Supported peripheral buses: General.
15RC7/RX/DTDigital_IOSignal terminal RC7/RX/DT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC7/RX/DT. Supported peripheral buses: General.
16VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
17VDDPower_InPrimary positive power supply input (VDD) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
18RB0/AN12/INT0Digital_IOSignal terminal RB0/AN12/INT0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB0/AN12/INT0. Supported peripheral buses: General.
19RB1/AN10/INT1Digital_IOSignal terminal RB1/AN10/INT1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB1/AN10/INT1. Supported peripheral buses: General.
20RB2/AN8/INT2/VMODigital_IOSignal terminal RB2/AN8/INT2/VMO (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB2/AN8/INT2/VMO. Supported peripheral buses: General.
21RB3/AN9/VPODigital_IOSignal terminal RB3/AN9/VPO (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB3/AN9/VPO. Supported peripheral buses: General.
22RB4/AN11/KBI0Digital_IOSignal terminal RB4/AN11/KBI0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB4/AN11/KBI0. Supported peripheral buses: General.
23RB5/KBI1/PGMDigital_IOSignal terminal RB5/KBI1/PGM (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB5/KBI1/PGM. Supported peripheral buses: General.
24RB6/KBI2/PGCDigital_IOSignal terminal RB6/KBI2/PGC (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB6/KBI2/PGC. Supported peripheral buses: General.
25RB7/KBI3/PGDDigital_IOSignal terminal RB7/KBI3/PGD (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB7/KBI3/PGD. Supported peripheral buses: General.
26MCLR#/VPP/RE3Digital_IOSignal terminal MCLR#/VPP/RE3 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: MCLR#/VPP/RE3. Supported peripheral buses: General.
27RA0/AN0Digital_IOSignal terminal RA0/AN0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA0/AN0. Supported peripheral buses: General.
28RA1/AN1Digital_IOSignal terminal RA1/AN1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA1/AN1. Supported peripheral buses: General.
29EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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