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PIC18F26K40T-I/SO (SOIC-28-300mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC18F26K40T-I/SO

MICROCHIPSOIC-28-300mil · 28 Pins · Pitch 1.27mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC18F26K40T-I/SO (SOIC-28-300mil)1#MCLR/VPP/RE2RA03RA14RA25RA36RA47RA58VSS9RA710RA611RC012RC113RC214RC328RB7/ICSPDAT27RB6/ICSPCLK26RB625RB424RB323RB222RB121RB020VDD19VSS18RC717RC616RC515RC4Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.822.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728E=7.50mm · Pitch e=1.27mmD=17.90mm-10-8-6-4-20246810131197531-1-3-5-7-9-11-13mm
3. 3D CAD MODEL
Package Body: 7.50mm × 17.90mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (28/28)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1#MCLR/VPP/RE3I/OMultiplexed I/O & Peripheral Pin #MCLR/VPP/RE3 (General)
2RA0I/OMultiplexed I/O & Peripheral Pin RA0 (General)
3RA1I/OMultiplexed I/O & Peripheral Pin RA1 (General)
4RA2I/OMultiplexed I/O & Peripheral Pin RA2 (General)
5RA3I/OMultiplexed I/O & Peripheral Pin RA3 (General)
6RA4I/OMultiplexed I/O & Peripheral Pin RA4 (General)
7RA5I/OMultiplexed I/O & Peripheral Pin RA5 (General)
8VSSGNDGround Reference Pin (VSS)
9RA7I/OMultiplexed I/O & Peripheral Pin RA7 (General)
10RA6I/OMultiplexed I/O & Peripheral Pin RA6 (General)
11RC0I/OMultiplexed I/O & Peripheral Pin RC0 (General)
12RC1I/OMultiplexed I/O & Peripheral Pin RC1 (General)
13RC2I/OMultiplexed I/O & Peripheral Pin RC2 (General)
14RC3I/OMultiplexed I/O & Peripheral Pin RC3 (General)
15RC4I/OMultiplexed I/O & Peripheral Pin RC4 (General)
16RC5I/OMultiplexed I/O & Peripheral Pin RC5 (General)
17RC6I/OMultiplexed I/O & Peripheral Pin RC6 (General)
18RC7I/OMultiplexed I/O & Peripheral Pin RC7 (General)
19VSSGNDGround Reference Pin (VSS)
20VDDPowerPower Supply Input (VDD — 2.7V-3.3V)
21RB0I/OMultiplexed I/O & Peripheral Pin RB0 (General)
22RB1I/OMultiplexed I/O & Peripheral Pin RB1 (General)
23RB2I/OMultiplexed I/O & Peripheral Pin RB2 (General)
24RB3I/OMultiplexed I/O & Peripheral Pin RB3 (General)
25RB4I/OMultiplexed I/O & Peripheral Pin RB4 (General)
26RB6I/OMultiplexed I/O & Peripheral Pin RB6 (General)
27RB6/ICSPCLKI/OMultiplexed I/O & Peripheral Pin RB6/ICSPCLK (General)
28RB7/ICSPDATI/OMultiplexed I/O & Peripheral Pin RB7/ICSPDAT (General)
PIN 1 #MCLR/VPP/RE3
I/O
Multiplexed I/O & Peripheral Pin #MCLR/VPP/RE3 (General)
Design note: Signal terminal #MCLR/VPP/RE3 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: #MCLR/VPP/RE3. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
1. Realistic 3D PackageREPRESENTATIVE
PIC18F26K40T-I/SO (SOIC-28-300mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC18F26K40T-I/SO (SOIC-28-300mil) - 2. Standard Pinout (Top View)
True package pinout (28 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC18F26K40T-I/SO (SOIC-28-300mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC18F26K40T-I/SO (SOIC-28-300mil) - 4. Package Dimensions (D×E×A)
SOIC-28-300mil · 7.50×17.90mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC18F26K40T-I/SO (SOIC-28-300mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (28 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC18F26K40T-I/SO (SOIC-28-300mil) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for PIC18F26K40T / PIC16F767 / PIC16F777
P2 · p02_fig021356×834px
PIC18F26K40T-I/SO (SOIC-28-300mil) — 44 43 42 41 40 39 16 17
44 43 42 41 40 39 16 17
P2 · p02_fig031352×990px
PIC18F26K40T-I/SO (SOIC-28-300mil) — PIC16F767
PIC16F767
P89 · p89_fig01867×606px
PIC18F26K40T-I/SO (SOIC-28-300mil) — FIGURE 9-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
FIGURE 9-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
P89 · p89_fig02867×775px
PIC18F26K40T-I/SO (SOIC-28-300mil) — FIGURE 9-2: COMPARE MODE OPERATION BLOCK DIAGRAM
FIGURE 9-2: COMPARE MODE OPERATION BLOCK DIAGRAM
P97 · p97_fig011777×938px
PIC18F26K40T-I/SO (SOIC-28-300mil) — FIGURE 10-2: SPI MASTER/SLAVE CONNECTION
FIGURE 10-2: SPI MASTER/SLAVE CONNECTION
P108 · p108_fig01738×2217px
PIC18F26K40T-I/SO (SOIC-28-300mil) — FIGURE 10-8: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
FIGURE 10-8: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
P109 · p109_fig011085×2300px
PIC18F26K40T-I/SO (SOIC-28-300mil) — FIGURE 10-9: I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
FIGURE 10-9: I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
P109 · p109_fig01P109
PIC18F26K40T-I/SO (SOIC-28-300mil) — Datasheet Page 109 (p109_fig01)
Datasheet Page 109 (p109_fig01)
P249 · p249_fig011777×2564px
PIC18F26K40T-I/SO (SOIC-28-300mil) — PIC16F7X7
PIC16F7X7
P2 · p02_fig01All Packages in PDF
PIC18F26K40T-I/SO (SOIC-28-300mil) — QFN (28-pin)
QFN (28-pin)

Technical Specifications & Part Details (PIC18F26K40T-I/SO)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC18F26K40T-I/SO (SOIC-28-300mil) is a 28-pin standard electronic & interconnect component featuring a 17.90 × 7.50 × 2.70 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 2.7V-3.3V supply operation across -40°C to +85°C with integrated SPI, I2C, ADC, PWM interfaces.
Operating Supply VoltageV_CC / V_DD
2.7V-3.3V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
1 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
17.90 × 7.50 × 2.70 mm (A1=0.20 mm)
Package family: SOIC (SOIC-28-300mil)
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, I2C, ADC, PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol28 auto-grouped pins
OK
IPC-7351B Land Pattern28 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — PIC18F26K40T / PIC16F767 / PIC16F777 (3)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (SOIC-28-300mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
17.90 × 7.50 mm
Height (A) & Pitch (e)IPC-7351B
A=2.70mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.90 mm
Pins / Total PadsTopology
28P / 28Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOIC-28-300mil
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC18F26K40T-I/SO (SOIC-28-300mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC18F26K40T-I/SO (SOIC-28-300mil)?

Manufactured by MICROCHIP, the PIC18F26K40T-I/SO is housed in a SOIC-28-300mil package with 28 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 2.7V-3.3V. Key pins include: 1 (#MCLR/VPP/RE3: Multiplexed I/O & Peripheral Pin #MCLR/VPP/RE3 (General)), 2 (RA0: Multiplexed I/O & Peripheral Pin RA0 (General)), 3 (RA1: Multiplexed I/O & Peripheral Pin RA1 (General)), 4 (RA2: Multiplexed I/O & Peripheral Pin RA2 (General)), 5 (RA3: Multiplexed I/O & Peripheral Pin RA3 (General)), 6 (RA4: Multiplexed I/O & Peripheral Pin RA4 (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC18F26K40T-I/SO?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC18F26K40T-I/SO (SOIC-28-300mil) has a nominal body envelope of 7.50 × 17.90 mm, pitch e = 1.27 mm, and 28 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC18F26K40T-I/SO?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC18F26K40T-I/SO (MICROCHIP, SOIC-28-300mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (28 pins) & PIC18F26K40T / PIC16F767 / PIC16F777 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1#MCLR/VPP/RE3Digital_IOSignal terminal #MCLR/VPP/RE3 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: #MCLR/VPP/RE3. Supported peripheral buses: General.
2RA0Digital_IOSignal terminal RA0 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RA0. Supported peripheral buses: General.
3RA1Digital_IOSignal terminal RA1 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RA1. Supported peripheral buses: General.
4RA2Digital_IOSignal terminal RA2 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RA2. Supported peripheral buses: General.
5RA3Digital_IOSignal terminal RA3 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RA3. Supported peripheral buses: General.
6RA4Digital_IOSignal terminal RA4 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RA4. Supported peripheral buses: General.
7RA5Digital_IOSignal terminal RA5 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RA5. Supported peripheral buses: General.
8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
9RA7Digital_IOSignal terminal RA7 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RA7. Supported peripheral buses: General.
10RA6Digital_IOSignal terminal RA6 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RA6. Supported peripheral buses: General.
11RC0Digital_IOSignal terminal RC0 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RC0. Supported peripheral buses: General.
12RC1Digital_IOSignal terminal RC1 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RC1. Supported peripheral buses: General.
13RC2Digital_IOSignal terminal RC2 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RC2. Supported peripheral buses: General.
14RC3Digital_IOSignal terminal RC3 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RC3. Supported peripheral buses: General.
15RC4Digital_IOSignal terminal RC4 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RC4. Supported peripheral buses: General.
16RC5Digital_IOSignal terminal RC5 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RC5. Supported peripheral buses: General.
17RC6Digital_IOSignal terminal RC6 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RC6. Supported peripheral buses: General.
18RC7Digital_IOSignal terminal RC7 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RC7. Supported peripheral buses: General.
19VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
20VDDPower_InPrimary positive power supply input (VDD) operating in the 2.7V-3.3V domain (Max rating: 3.3V).
21RB0Digital_IOSignal terminal RB0 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RB0. Supported peripheral buses: General.
22RB1Digital_IOSignal terminal RB1 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RB1. Supported peripheral buses: General.
23RB2Digital_IOSignal terminal RB2 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RB2. Supported peripheral buses: General.
24RB3Digital_IOSignal terminal RB3 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RB3. Supported peripheral buses: General.
25RB4Digital_IOSignal terminal RB4 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RB4. Supported peripheral buses: General.
26RB6Digital_IOSignal terminal RB6 (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RB6. Supported peripheral buses: General.
27RB6/ICSPCLKDigital_IOSignal terminal RB6/ICSPCLK (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RB6/ICSPCLK. Supported peripheral buses: General.
28RB7/ICSPDATDigital_IOSignal terminal RB7/ICSPDAT (I/O, 2.7V-3.3V domain). Multiplexed alternate functions: RB7/ICSPDAT. Supported peripheral buses: General.
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