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MCP2200-I/MQ (VQFN-20-EP(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

MCP2200-I/MQ

MICROCHIPID: C219241VQFN-20-EP(5x5) · 21 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · MCP2200-I/MQ (VQFN-20-EP(5x5))1RST2GP7/TxLED3GP6/RxLED4GP55GP46GP37Tx8RTS9Rx10CTS11GP221EP20OSC219OSC118VDD17VSS16D+15D -14Vusb13GP0/SSPND12GP1/USB - CFGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.820.315.210.25.10-5.1-10.2-15.2-20.3mm
2. 2D FOOTPRINT
123456789101112131415161718192021E=5.00mm · Pitch e=0.50mmD=5.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (21/21)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RSTI/OMultiplexed I/O & Peripheral Pin RST (General)
2GP7/TxLEDI/OMultiplexed I/O & Peripheral Pin GP7/TxLED (USB)
3GP6/RxLEDI/OMultiplexed I/O & Peripheral Pin GP6/RxLED (USB)
4GP5I/OMultiplexed I/O & Peripheral Pin GP5 (General)
5GP4I/OMultiplexed I/O & Peripheral Pin GP4 (General)
6GP3I/OMultiplexed I/O & Peripheral Pin GP3 (General)
7TxI/OMultiplexed I/O & Peripheral Pin Tx (UART)
8RTSI/OMultiplexed I/O & Peripheral Pin RTS (UART)
9RxI/OMultiplexed I/O & Peripheral Pin Rx (UART)
10CTSI/OMultiplexed I/O & Peripheral Pin CTS (UART)
11GP2I/OMultiplexed I/O & Peripheral Pin GP2 (General)
12GP1/USB - CFGI/OMultiplexed I/O & Peripheral Pin GP1/USB - CFG (USB)
13GP0/SSPNDI/OMultiplexed I/O & Peripheral Pin GP0/SSPND (USB)
14VusbI/OMultiplexed I/O & Peripheral Pin Vusb (USB)
15D -I/OMultiplexed I/O & Peripheral Pin D - (USB)
16D+I/OMultiplexed I/O & Peripheral Pin D+ (USB)
17VSSGNDGround Reference Pin (VSS)
18VDDPowerPower Supply Input (VDD — 3.0V-5.5V)
19OSC1I/OMultiplexed I/O & Peripheral Pin OSC1 (RTC/CLK)
20OSC2I/OMultiplexed I/O & Peripheral Pin OSC2 (RTC/CLK)
21EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 RST
I/O
Multiplexed I/O & Peripheral Pin RST (General)
Design note: Resetinputmustbeexternallybiased
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 20 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: MCP2200-I/MQ (MICROCHIP · VQFN-20-EP(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
MCP2200-I/MQ (VQFN-20-EP(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
MCP2200-I/MQ (VQFN-20-EP(5x5)) - 2. Standard Pinout (Top View)
True package pinout (21 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
MCP2200-I/MQ (VQFN-20-EP(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
MCP2200-I/MQ (VQFN-20-EP(5x5)) - 4. Package Dimensions (D×E×A)
VQFN-20-EP(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
MCP2200-I/MQ (VQFN-20-EP(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (21 Pads)Expand ›
6. Application SchematicSCHEMATIC
MCP2200-I/MQ (VQFN-20-EP(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (20 figures · Page 1/2)
Showing 1–12 of 20 uncropped original figures for MCP2200
P1 · p01_fig01377×200px
MCP2200-I/MQ (VQFN-20-EP(5x5)) — USB 2.0 to UART Protocol Converter with GPIO
USB 2.0 to UART Protocol Converter with GPIO
P2 · p02_fig011777×1682px
MCP2200-I/MQ (VQFN-20-EP(5x5)) — MCP2200 | Block Diagram | UART Controller USB Protocol | Controller | USB Transceiver | 3.3V LDO | Configuration & Control Registers | OSC Reset | Control | USB Clock State Clock | GPIO | Baud Generator | VSS | VUSB | RST VSS VDD | Rx | Tx
MCP2200 | Block Diagram | UART Controller USB Protocol | Controller | USB Transceiver | 3.3V LDO | Configuration & Control Registers | OSC Reset | Control | USB Clock State Clock | GPIO | Baud Generator | VSS | VUSB | RST VSS VDD | Rx | Tx
P7 · p07_fig011777×1237px
MCP2200-I/MQ (VQFN-20-EP(5x5)) — FIGURE 1-4: TYPICAL POWER SUPPLY OPTION USING THE 5V PROVIDED BY THE USB
FIGURE 1-4: TYPICAL POWER SUPPLY OPTION USING THE 5V PROVIDED BY THE USB
P7 · p07_fig01P7
MCP2200-I/MQ (VQFN-20-EP(5x5)) — Datasheet Page 7 (p07_fig01)
Datasheet Page 7 (p07_fig01)
P8 · p08_fig01867×620px
MCP2200-I/MQ (VQFN-20-EP(5x5)) — FIGURE 1-6: CONNECTING THE RST PIN IN A SELF-POWERED CONFIGURATION (RECOMMENDED) VBUS
FIGURE 1-6: CONNECTING THE RST PIN IN A SELF-POWERED CONFIGURATION (RECOMMENDED) VBUS
P9 · p09_fig01867×837px
MCP2200-I/MQ (VQFN-20-EP(5x5)) — FIGURE 1-8: CERAMIC RESONATOR OPERATION
FIGURE 1-8: CERAMIC RESONATOR OPERATION
P9 · p09_fig02867×679px
MCP2200-I/MQ (VQFN-20-EP(5x5)) — FIGURE 1-8: CERAMIC RESONATOR OPERATION
FIGURE 1-8: CERAMIC RESONATOR OPERATION
P9 · p09_fig01P9
MCP2200-I/MQ (VQFN-20-EP(5x5)) — Datasheet Page 9 (p09_fig01)
Datasheet Page 9 (p09_fig01)
P32 · p32_fig011777×2564px
MCP2200-I/MQ (VQFN-20-EP(5x5)) — MCP2200
MCP2200
P32 · p32_fig02326×310px
MCP2200-I/MQ (VQFN-20-EP(5x5)) — 20-lead VQFN (05x05 mm) Example:
20-lead VQFN (05x05 mm) Example:
P32 · p32_fig03341×324px
MCP2200-I/MQ (VQFN-20-EP(5x5)) — 20-lead VQFN (05x05 mm) Example:
20-lead VQFN (05x05 mm) Example:
P32 · p32_fig06380×375px
MCP2200-I/MQ (VQFN-20-EP(5x5)) — 20-Lead SSOP Example:
20-Lead SSOP Example:
Page 1 / 2 (20 extracted figures)

Technical Specifications & Part Details (MCP2200-I/MQ)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:MCP2200-I/MQ (VQFN-20-EP(5x5)) is a 20-pin standard electronic & interconnect component featuring a 5.00 × 5.00 × 1.00 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V-5.5V supply operation across 40°C to +85°C with integrated USB, UART, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V-5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
12 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 1.00 mm (A1=0.03 mm)
Package family: QFN (VQFN-20-EP(5x5))
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol21 auto-grouped pins
OK
IPC-7351B Land Pattern21 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 3.20×3.20mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (VQFN-20-EP(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 1.00 mm
Pins / Total PadsTopology
21P / 21Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
VQFN-20-EP(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MCP2200-I/MQ (VQFN-20-EP(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MCP2200-I/MQ (VQFN-20-EP(5x5))?

Manufactured by MICROCHIP, the MCP2200-I/MQ is housed in a VQFN-20-EP(5x5) package with 21 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 3.0V-5.5V. Key pins include: 1 (RST: Multiplexed I/O & Peripheral Pin RST (General)), 2 (GP7/TxLED: Multiplexed I/O & Peripheral Pin GP7/TxLED (USB)), 3 (GP6/RxLED: Multiplexed I/O & Peripheral Pin GP6/RxLED (USB)), 4 (GP5: Multiplexed I/O & Peripheral Pin GP5 (General)), 5 (GP4: Multiplexed I/O & Peripheral Pin GP4 (General)), 6 (GP3: Multiplexed I/O & Peripheral Pin GP3 (General)).

What are the IPC-7351B PCB Footprint dimensions for MCP2200-I/MQ?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MCP2200-I/MQ (VQFN-20-EP(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 3.20 × 3.20 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MCP2200-I/MQ?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MCP2200-I/MQ (MICROCHIP, VQFN-20-EP(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (21 pins) & MCP2200 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RSTDigital_IOSignal terminal RST (I/O, 3.0V-5.5V domain). Multiplexed alternate functions: RST. Supported peripheral buses: General.
2GP7/TxLEDDigital_IOSignal terminal GP7/TxLED (I/O, 3.0V-5.5V domain). Multiplexed alternate functions: GP7/TxLED. Supported peripheral buses: USB.
3GP6/RxLEDDigital_IOSignal terminal GP6/RxLED (I/O, 3.0V-5.5V domain). Multiplexed alternate functions: GP6/RxLED. Supported peripheral buses: USB.
4GP5Digital_IOSignal terminal GP5 (I/O, 3.0V-5.5V domain). Multiplexed alternate functions: GP5. Supported peripheral buses: General.
5GP4Digital_IOSignal terminal GP4 (I/O, 3.0V-5.5V domain). Multiplexed alternate functions: GP4. Supported peripheral buses: General.
6GP3Digital_IOSignal terminal GP3 (I/O, 3.0V-5.5V domain). Multiplexed alternate functions: GP3. Supported peripheral buses: General.
7TxDigital_IOSignal terminal Tx (I/O, 3.0V-5.5V domain). Multiplexed alternate functions: Tx. Supported peripheral buses: UART.
8RTSDigital_IOSignal terminal RTS (I/O, 3.0V-5.5V domain). Multiplexed alternate functions: RTS. Supported peripheral buses: UART.
9RxDigital_IOSignal terminal Rx (I/O, 3.0V-5.5V domain). Multiplexed alternate functions: Rx. Supported peripheral buses: UART.
10CTSDigital_IOSignal terminal CTS (I/O, 3.0V-5.5V domain). Multiplexed alternate functions: CTS. Supported peripheral buses: UART.
11GP2Digital_IOSignal terminal GP2 (I/O, 3.0V-5.5V domain). Multiplexed alternate functions: GP2. Supported peripheral buses: General.
12GP1/USB - CFGDigital_IOSignal terminal GP1/USB - CFG (I/O, 3.0V-5.5V domain). Multiplexed alternate functions: GP1/USB - CFG. Supported peripheral buses: USB.
13GP0/SSPNDDigital_IOSignal terminal GP0/SSPND (I/O, 3.0V-5.5V domain). Multiplexed alternate functions: GP0/SSPND. Supported peripheral buses: USB.
14VusbDigital_IOSignal terminal Vusb (I/O, 3.0V-5.5V domain). Multiplexed alternate functions: Vusb. Supported peripheral buses: USB.
15D -Digital_IOSignal terminal D - (I/O, 3.0V-5.5V domain). Multiplexed alternate functions: D -. Supported peripheral buses: USB.
16D+Digital_IOSignal terminal D+ (I/O, 3.0V-5.5V domain). Multiplexed alternate functions: D+. Supported peripheral buses: USB.
17VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
18VDDPower_InPrimary positive power supply input (VDD) operating in the 3.0V-5.5V domain (Max rating: 5.5V).
19OSC1Digital_IOSignal terminal OSC1 (I/O, 3.0V-5.5V domain). Multiplexed alternate functions: OSC1. Supported peripheral buses: RTC/CLK.
20OSC2Digital_IOSignal terminal OSC2 (I/O, 3.0V-5.5V domain). Multiplexed alternate functions: OSC2. Supported peripheral buses: RTC/CLK.
21EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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