ATSAM4S2AA-MU (QFN-48-EP(7x7)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of ATSAM4S2AA-MU (QFN-48-EP(7x7))?

Manufactured by MICROCHIP, the ATSAM4S2AA-MU is housed in a QFN-48-EP(7x7) package with 49 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.62V to 3.6V. Key pins include: 1 (ADVREF: Multiplexed I/O & Peripheral Pin ADVREF (General)), 2 (GND: Ground Reference Pin (GND)), 3 (PB0/AD4: Multiplexed I/O & Peripheral Pin PB0/AD4 (General)), 4 (PB4: Multiplexed I/O & Peripheral Pin PB4 (General)), 5 (PB5: Multiplexed I/O & Peripheral Pin PB5 (General)), 6 (PB6: Multiplexed I/O & Peripheral Pin PB6 (SWD/JTAG)).

Q: What are the IPC-7351B PCB Footprint dimensions for ATSAM4S2AA-MU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATSAM4S2AA-MU (QFN-48-EP(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 5.10 × 5.10 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATSAM4S2AA-MU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATSAM4S2AA-MU (MICROCHIP, QFN-48-EP(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	ADVREF	Analog	Multiplexed I/O & Peripheral Pin ADVREF (General)
2	GND	GND	Ground Reference Pin (GND)
3	PB0/AD4	I/O	Multiplexed I/O & Peripheral Pin PB0/AD4 (General)
4	PB4	I/O	Multiplexed I/O & Peripheral Pin PB4 (General)
5	PB5	I/O	Multiplexed I/O & Peripheral Pin PB5 (General)
6	PB6	I/O	Multiplexed I/O & Peripheral Pin PB6 (SWD/JTAG)
7	PB7	I/O	Multiplexed I/O & Peripheral Pin PB7 (SWD/JTAG)
8	VDDOUT	Power	Power Supply Input (VDDOUT — 1.62V to 3.6V)
9	PA17/PGMD5/AD0	I/O	Multiplexed I/O & Peripheral Pin PA17/PGMD5/AD0 (General)
10	PB10	I/O	Multiplexed I/O & Peripheral Pin PB10 (General)
11	PB11	I/O	Multiplexed I/O & Peripheral Pin PB11 (General)
12	PB12	I/O	Multiplexed I/O & Peripheral Pin PB12 (General)
13	VDDIO	Power	Power Supply Input (VDDIO — 1.62V to 3.6V)
14	PA16/PGMD4	I/O	Multiplexed I/O & Peripheral Pin PA16/PGMD4 (General)
15	PA15/PGMD3	I/O	Multiplexed I/O & Peripheral Pin PA15/PGMD3 (General)
16	PA14/PGMD2	I/O	Multiplexed I/O & Peripheral Pin PA14/PGMD2 (General)
17	PA13/PGMD1	I/O	Multiplexed I/O & Peripheral Pin PA13/PGMD1 (General)
18	VDDCORE	Power	Power Supply Input (VDDCORE — 1.62V to 3.6V)
19	PA12/PGMD0	I/O	Multiplexed I/O & Peripheral Pin PA12/PGMD0 (General)
20	PA11/PGMM3	I/O	Multiplexed I/O & Peripheral Pin PA11/PGMM3 (General)
21	PA10/PGMM2	I/O	Multiplexed I/O & Peripheral Pin PA10/PGMM2 (General)
22	PA9/PGMM1	I/O	Multiplexed I/O & Peripheral Pin PA9/PGMM1 (General)
23	PA8/XOUT32/PGMM0	I/O	Multiplexed I/O & Peripheral Pin PA8/XOUT32/PGMM0 (RTC/CLK)
24	PA7/XIN32/PGMNVALID	I/O	Multiplexed I/O & Peripheral Pin PA7/XIN32/PGMNVALID (RTC/CLK)
25	TDI/PB4	I/O	Multiplexed I/O & Peripheral Pin TDI/PB4 (General)
26	PA6/PGMNOE	I/O	Multiplexed I/O & Peripheral Pin PA6/PGMNOE (General)
27	PA5/PGMRDY	I/O	Multiplexed I/O & Peripheral Pin PA5/PGMRDY (General)
28	PA4/PGMNCMD	I/O	Multiplexed I/O & Peripheral Pin PA4/PGMNCMD (General)
29	NRST	I	System Enable & Hardware Reset (NRST)
30	TST	I/O	Multiplexed I/O & Peripheral Pin TST (General)
31	PA3	I/O	Multiplexed I/O & Peripheral Pin PA3 (General)
32	PA2/PGMEN2	I/O	Multiplexed I/O & Peripheral Pin PA2/PGMEN2 (General)
33	VDDIO	Power	Power Supply Input (VDDIO — 1.62V to 3.6V)
34	GND	GND	Ground Reference Pin (GND)
35	PA1/PGMEN1	I/O	Multiplexed I/O & Peripheral Pin PA1/PGMEN1 (General)
36	PA0/PGMEN0	I/O	Multiplexed I/O & Peripheral Pin PA0/PGMEN0 (General)
37	TDO/TRACESWO/PB5	I/O	Multiplexed I/O & Peripheral Pin TDO/TRACESWO/PB5 (General)
38	JTAGSEL	I/O	Multiplexed I/O & Peripheral Pin JTAGSEL (SWD/JTAG)
39	TMS/SWDIO/PB6	I/O	Multiplexed I/O & Peripheral Pin TMS/SWDIO/PB6 (SWD/JTAG)
40	TCK/SWCLK/PB7	I/O	Multiplexed I/O & Peripheral Pin TCK/SWCLK/PB7 (SWD/JTAG)
41	VDDCORE	Power	Power Supply Input (VDDCORE — 1.62V to 3.6V)
42	ERASE/PB12	I/O	Multiplexed I/O & Peripheral Pin ERASE/PB12 (General)
43	DDM/PB10	I/O	Multiplexed I/O & Peripheral Pin DDM/PB10 (General)
44	DDP/PB11	I/O	Multiplexed I/O & Peripheral Pin DDP/PB11 (General)
45	XOUT/PB8	I/O	Multiplexed I/O & Peripheral Pin XOUT/PB8 (RTC/CLK)
46	XIN/PB9/PGMCK	I/O	Multiplexed I/O & Peripheral Pin XIN/PB9/PGMCK (RTC/CLK)
47	VDDIO	Power	Power Supply Input (VDDIO — 1.62V to 3.6V)
48	VDDPLL	Power	Power Supply Input (VDDPLL — 1.62V to 3.6V)
49	EP	GND	Exposed Thermal & Ground Pad (EP)

PIN 1 ADVREF

Analog

Multiplexed I/O & Peripheral Pin ADVREF (General)

Design note: Signal terminal ADVREF (Analog, 1.62V to 3.6V domain). Multiplexed alternate functions: ADVREF. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

ATSAM4S2AA-MU (QFN-48-EP(7x7)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

ATSAM4S2AA-MU (QFN-48-EP(7x7)) - 2. Standard Pinout (Top View)

True package pinout (49 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

ATSAM4S2AA-MU (QFN-48-EP(7x7)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

ATSAM4S2AA-MU (QFN-48-EP(7x7)) - 4. Package Dimensions (D×E×A)

QFN-48-EP(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

ATSAM4S2AA-MU (QFN-48-EP(7x7)) - 5. Recommended Land Pattern

IPC-7351B Footprint (49 Pads)Expand ›

6. Application SchematicSCHEMATIC

ATSAM4S2AA-MU (QFN-48-EP(7x7)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)

Showing 1–8 of 8 uncropped original figures for ATSAM4S2AA

P18 · p18_fig01634×765px

Figure 4-3. Orientation of the 100-ball VFBGA Package

P25 · p25_fig01592×575px

Figure 4-7. Orientation of the 48-lead LQFP Package

P25 · p25_fig021392×726px

Figure 4-8. Orientation of the 48-lead QFN Package

P25 · p25_fig02P25

Datasheet Page 25 (p25_fig02)

P806 · p806_fig01902×533px

Figure 36-35. Typical Connection to a RS485 Bus

P806 · p806_fig021250×717px

Figure 36-36. Example of RTS Drive with Timeguard

P806 · p806_fig01P806

Datasheet Page 806 (p806_fig01)

P1030 · p1030_fig011590×570px

Figure 40-2. Board Schematic to Interface Device Peripheral

Technical Specifications & Part Details (ATSAM4S2AA-MU)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:ATSAM4S2AA-MU (QFN-48-EP(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.62V to 3.6V supply operation across -40°C to 105°C with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, IrDA, RTC/CLK, SWD/JTAG interfaces.

Operating Supply VoltageV_CC / V_DD

1.62V to 3.6V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to 105°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

120 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

7.00 × 7.00 × 0.85 mm (A1=0.03 mm)

Package family: QFN (QFN-48-EP(7x7))

Pin Count & Lead PitchN / e

48 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, IrDA, RTC/CLK, SWD/JTAG

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol49 auto-grouped pins

IPC-7351B Land Pattern49 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteEPAD 5.10×5.10mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-48-EP(7x7))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

7.00 × 7.00 mm

Height (A) & Pitch (e)IPC-7351B

A=0.85mm · e=0.50mm

Pad Size (W × L)Level B

0.28 × 0.80 mm

Pins / Total PadsTopology

49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit QFN-48-EP(7x7)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ATSAM4S2AA-MU (QFN-48-EP(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ATSAM4S2AA-MU (QFN-48-EP(7x7))?

Manufactured by MICROCHIP, the ATSAM4S2AA-MU is housed in a QFN-48-EP(7x7) package with 49 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.62V to 3.6V. Key pins include: 1 (ADVREF: Multiplexed I/O & Peripheral Pin ADVREF (General)), 2 (GND: Ground Reference Pin (GND)), 3 (PB0/AD4: Multiplexed I/O & Peripheral Pin PB0/AD4 (General)), 4 (PB4: Multiplexed I/O & Peripheral Pin PB4 (General)), 5 (PB5: Multiplexed I/O & Peripheral Pin PB5 (General)), 6 (PB6: Multiplexed I/O & Peripheral Pin PB6 (SWD/JTAG)).

What are the IPC-7351B PCB Footprint dimensions for ATSAM4S2AA-MU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATSAM4S2AA-MU (QFN-48-EP(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 5.10 × 5.10 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATSAM4S2AA-MU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATSAM4S2AA-MU (MICROCHIP, QFN-48-EP(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & ATSAM4S2AA Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	ADVREF	Analog	Signal terminal ADVREF (Analog, 1.62V to 3.6V domain). Multiplexed alternate functions: ADVREF. Supported peripheral buses: General.
2	GND	GND	0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
3	PB0/AD4	Digital_IO	Signal terminal PB0/AD4 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PB0/AD4. Supported peripheral buses: General.
4	PB4	Digital_IO	Signal terminal PB4 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
5	PB5	Digital_IO	Signal terminal PB5 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
6	PB6	Digital_IO	Signal terminal PB6 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PB6. Supported peripheral buses: SWD/JTAG.
7	PB7	Digital_IO	Signal terminal PB7 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PB7. Supported peripheral buses: SWD/JTAG.
8	VDDOUT	Power_In	Primary positive power supply input (VDDOUT) operating in the 1.62V to 3.6V domain (Max rating: 3.6V).
9	PA17/PGMD5/AD0	Digital_IO	Signal terminal PA17/PGMD5/AD0 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PA17/PGMD5/AD0. Supported peripheral buses: General.
10	PB10	Digital_IO	Signal terminal PB10 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
11	PB11	Digital_IO	Signal terminal PB11 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
12	PB12	Digital_IO	Signal terminal PB12 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
13	VDDIO	Power_In	Primary positive power supply input (VDDIO) operating in the 1.62V to 3.6V domain (Max rating: 3.6V).
14	PA16/PGMD4	Digital_IO	Signal terminal PA16/PGMD4 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PA16/PGMD4. Supported peripheral buses: General.
15	PA15/PGMD3	Digital_IO	Signal terminal PA15/PGMD3 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PA15/PGMD3. Supported peripheral buses: General.
16	PA14/PGMD2	Digital_IO	Signal terminal PA14/PGMD2 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PA14/PGMD2. Supported peripheral buses: General.
17	PA13/PGMD1	Digital_IO	Signal terminal PA13/PGMD1 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PA13/PGMD1. Supported peripheral buses: General.
18	VDDCORE	Power_In	Primary positive power supply input (VDDCORE) operating in the 1.62V to 3.6V domain (Max rating: 3.6V).
19	PA12/PGMD0	Digital_IO	Signal terminal PA12/PGMD0 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PA12/PGMD0. Supported peripheral buses: General.
20	PA11/PGMM3	Digital_IO	Signal terminal PA11/PGMM3 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PA11/PGMM3. Supported peripheral buses: General.
21	PA10/PGMM2	Digital_IO	Signal terminal PA10/PGMM2 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PA10/PGMM2. Supported peripheral buses: General.
22	PA9/PGMM1	Digital_IO	Signal terminal PA9/PGMM1 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PA9/PGMM1. Supported peripheral buses: General.
23	PA8/XOUT32/PGMM0	Digital_IO	Signal terminal PA8/XOUT32/PGMM0 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PA8/XOUT32/PGMM0. Supported peripheral buses: RTC/CLK.
24	PA7/XIN32/PGMNVALID	Digital_IO	Signal terminal PA7/XIN32/PGMNVALID (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PA7/XIN32/PGMNVALID. Supported peripheral buses: RTC/CLK.
25	TDI/PB4	Digital_IO	Signal terminal TDI/PB4 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: TDI/PB4. Supported peripheral buses: General.
26	PA6/PGMNOE	Digital_IO	Signal terminal PA6/PGMNOE (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PA6/PGMNOE. Supported peripheral buses: General.
27	PA5/PGMRDY	Digital_IO	Signal terminal PA5/PGMRDY (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PA5/PGMRDY. Supported peripheral buses: General.
28	PA4/PGMNCMD	Digital_IO	Signal terminal PA4/PGMNCMD (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PA4/PGMNCMD. Supported peripheral buses: General.
29	NRST	Digital_IO	Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
30	TST	Digital_IO	Signal terminal TST (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: TST. Supported peripheral buses: General.
31	PA3	Digital_IO	Signal terminal PA3 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
32	PA2/PGMEN2	Digital_IO	Signal terminal PA2/PGMEN2 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PA2/PGMEN2. Supported peripheral buses: General.
33	VDDIO	Power_In	Primary positive power supply input (VDDIO) operating in the 1.62V to 3.6V domain (Max rating: 3.6V).
34	GND	GND	0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
35	PA1/PGMEN1	Digital_IO	Signal terminal PA1/PGMEN1 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PA1/PGMEN1. Supported peripheral buses: General.
36	PA0/PGMEN0	Digital_IO	Signal terminal PA0/PGMEN0 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: PA0/PGMEN0. Supported peripheral buses: General.
37	TDO/TRACESWO/PB5	Digital_IO	Signal terminal TDO/TRACESWO/PB5 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: TDO/TRACESWO/PB5. Supported peripheral buses: General.
38	JTAGSEL	Digital_IO	Signal terminal JTAGSEL (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: JTAGSEL. Supported peripheral buses: SWD/JTAG.
39	TMS/SWDIO/PB6	Digital_IO	Signal terminal TMS/SWDIO/PB6 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: TMS/SWDIO/PB6. Supported peripheral buses: SWD/JTAG.
40	TCK/SWCLK/PB7	Digital_IO	Signal terminal TCK/SWCLK/PB7 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: TCK/SWCLK/PB7. Supported peripheral buses: SWD/JTAG.
41	VDDCORE	Power_In	Primary positive power supply input (VDDCORE) operating in the 1.62V to 3.6V domain (Max rating: 3.6V).
42	ERASE/PB12	Digital_IO	Signal terminal ERASE/PB12 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: ERASE/PB12. Supported peripheral buses: General.
43	DDM/PB10	Digital_IO	Signal terminal DDM/PB10 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: DDM/PB10. Supported peripheral buses: General.
44	DDP/PB11	Digital_IO	Signal terminal DDP/PB11 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: DDP/PB11. Supported peripheral buses: General.
45	XOUT/PB8	Digital_IO	Signal terminal XOUT/PB8 (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: XOUT/PB8. Supported peripheral buses: RTC/CLK.
46	XIN/PB9/PGMCK	Digital_IO	Signal terminal XIN/PB9/PGMCK (I/O, 1.62V to 3.6V domain). Multiplexed alternate functions: XIN/PB9/PGMCK. Supported peripheral buses: RTC/CLK.
47	VDDIO	Power_In	Primary positive power supply input (VDDIO) operating in the 1.62V to 3.6V domain (Max rating: 3.6V).
48	VDDPLL	Power_In	Primary positive power supply input (VDDPLL) operating in the 1.62V to 3.6V domain (Max rating: 3.6V).
49	EP	GND	Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.

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