Mechanical Dimensions & Land Pattern (ESOP-8)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit ESOP-8 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — TP4056 (ESOP-8)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of TP4056 (ESOP-8)?
Manufactured by GOODWORK, the TP4056 is housed in a ESOP-8 package with 9 pins and a 1.27 mm lead pitch. Key pins include: 1 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 2 (PROG: Multiplexed I/O & Peripheral Pin PROG (General)), 3 (GND: Ground Reference Pin (GND)), 4 (VCC: Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)), 5 (BAT: Multiplexed I/O & Peripheral Pin BAT (General)), 6 (STDBY#: Multiplexed I/O & Peripheral Pin STDBY# (General)).
What are the IPC-7351B PCB Footprint dimensions for TP4056?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), TP4056 (ESOP-8) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 1.27 mm, and 9 copper pads plus a central exposed thermal pad (EPAD) of 2.40 × 3.10 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for TP4056?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for TP4056 (GOODWORK, ESOP-8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (9 pins) & TP4056 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | NC | Digital_IO | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 2 | PROG | Digital_IO | Signal terminal PROG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PROG. Supported peripheral buses: General. |
| 3 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 4 | VCC | Power_In | Primary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 5 | BAT | Digital_IO | Signal terminal BAT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BAT. Supported peripheral buses: General. |
| 6 | STDBY# | Digital_IO | Signal terminal STDBY# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: STDBY#. Supported peripheral buses: General. |
| 7 | CHRG# | Digital_IO | Signal terminal CHRG# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CHRG#. Supported peripheral buses: General. |
| 8 | NC | Digital_IO | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 9 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |